SLUAA61B September 2022 – November 2022 UCC27282-Q1 , UCC27284-Q1
1.3.1 SOIC Package
Figure 1-3 shows the UCC27282-Q1 UCC27284-Q1pin diagram for the SOIC package. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the UCC27282-Q1 UCC27284-Q1 datasheet.
Figure 1-3 Pin
Diagram (SOIC
Package)Table 1-8 Pin
FMA for Device Pins Short-Circuited to
Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | LO will remain low. HO will remain low. | B |
| HB | 2 | Device may be damaged with unknown LO/HO state | A |
| HO | 3 | Device may be damaged with unknown LO/HO state | A |
| HS | 4 | Device may be damaged with unknown LO/HO state | A |
| HI | 5 | HO will be in a low state | B |
| LI | 6 | LO will be a low state | B |
| VSS | 7 | N/A | D |
| LO | 8 | Device may be damaged with unknown LO/HO state | A |
Table 1-9 Pin
FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | LO will remain low. HO will remain low. | B |
| HB | 2 | HO will be pulled to HS potential | B |
| HO | 3 | HO terminal not connected to the system | D |
| HS | 4 | HO will be pulled to HB potential | B |
| HI | 5 | HO will be in a low state | B |
| LI | 6 | LO will be in a low state | B |
| VSS | 7 | HO will be in a low state LO will be pulled to VDD | B |
| LO | 8 | LO terminal not connected to the system | D |
Table 1-10 Pin
FMA for Device Pins Short-Circuited to Adjacent
Pin
| Pin Name | Pin No. | Shorted to (PIN#+1) | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| VDD | 1 | HB | Device may be damaged. LO/HO may be damaged with unknown state. | A |
| HB | 2 | HO | Device may be damaged with unknown HO state | A |
| HO | 3 | HS | Device may be damaged with unknown LO/HO state | A |
| HS | 4 | N/A | - | |
| HI | 5 | LI | HO/LO will be in a low state | B |
| LI | 6 | VSS | LO will be a low state | B |
| VSS | 7 | LO | Device may be damaged with unknown LO/HO state | A |
| LO | 8 | N/A | - |
Table 1-11 Pin FMA for Device Pins Short-Circuited to
supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| VDD | 1 | No effect | D |
| HB | 2 | Device may be damaged with unknown LO/HO state | A |
| HO | 3 | Device may be damaged with unknown LO/HO state | A |
| HS | 4 | Device may be damaged with unknown LO/HO state | A |
| HI | 5 | Short to 5V (Power supply of the Microcontroller) LO/HO will follow the interlock truth table depending on LI/HI | B |
| LI | 6 | Short to 5V (Power supply of the Microcontroller) LO/HO will follow the interlock truth table depending on LI/HI | B |
| VSS | 7 | HO will be in a low state LO will be pulled to VDD | B |
| LO | 8 | Device may be damaged with unknown LO/HO state | A |