SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

1 Introduction

The configuration process described in this document writes to the NVM space and is intended to be used in a production line or development setting. This mechanism is not intended to be used in applications since the process impacts the regulator outputs and GPIO functions.

The Scalable PMIC GUI provides a mechanism to generate a binary image which can, in turn, be uploaded to the NVM of the PMIC. The binary is generated from the NVM programming page by selecting Save as Binary Code, as shown in Figure 1-1. See the Scalable PMIC's GUI User’s Guide for instructions on configuring the PMIC and generating an image from that configuration.

GUID-20211013-SS0I-RSW4-DKBK-RHTFFQP6JBF0-low.svg Figure 1-1 Generating a Binary File From the Scalable PMIC GUI

Table 1-1 shows examples of entries in the binary file. Each row consists of the page information, the register address, and the data.

Table 1-1 GUI Binary Output Format
Binary Row Description
0x0004 = 0xa0 Page 0 entries
0x00d1 = 0x00
0x0100 = 0x02 Page 1 entries
0x014A = 0x06
0x3000 = 0x0A Page 3 entries
0x32ff = 0x00
0x405 = 0xff Page 4 entries
0x409 = 0xff