SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

A Registers Backed by NVM

While the NVM space is continuous, write to only the registers described in Table 8-1 for NVM updates.

Table A-1 TPS6594-Q1 and TPS6593-Q1 NVM Backed Registers
Page 0 Page 14 Page32 Page 4
0x04-0x20 0x01 0x00-0xFF 0x05
0x23-0x2C 0x03- 0x0A 0x00-0xFF 0x09
0x31-0x3E 0x0C- 0x14 0x00-0xFF
0x41-0x54 0x16- 0x281
0x56-0x59 0x33 - 0x35
0x78-0x7E 0x3F - 0x405
0x84 0x42 - 0x43
0x87-0x88 0x45 - 0x4A
0x8A- 0x8E
0x92
0x9B
0xA7
0xC3
0xCD-0xD1
0xF0 - 0xFB3
(1) When the serial interface is changed, the recommendation is to handle page 1 addresses 0x18, 0x22, and 0x23 immediately after the NVM is unlocked.
(2) Page 3 sub-page address control is described in PFSM.
(3) The content stored in address 0xF0 through 0xFB is related to the register CRC and is described in Updating the Register CRC.
(4) Page 1 registers 0x00, 0x02, 0x0B, 0x15, 0xA8, 0xB1, 0xBA, 0xC3, and 0xCC are not to be changed from the factory settings.
(5) Page 1 register 0x41 is described in Section 5.4
Table A-2 LP876x-Q1 NVM Backed Registers
Page 0 Page 14 Page 32 Page 4
0x04-0x0B 0x01 0x00-0xFF 0x05
0x0E-0x15 0x03-0x0A 0x00-0xFF 0x09
0x18-0x1B 0x0C-0x14
0x2B-0x3A 0x16-0x281
0x3C-0x3E 0x33-0x37
0x41 0x3F-0x405
0x43-0x4A 0x42-0x43
0x4E-0x54
0x56-0x59
0x78
0x7B-0x7D
0x84
0x87-0x88
0x8A-0x8B
0x8E
0x92
0xA7-0xA8
0xC3
0xCD-0xD0
0xF0-0xF93
(1) When the serial interface is changed, the recommendation is to handle page 1 addresses 0x18, 0x22, and 0x23 immediately after the NVM is unlocked.
(2) Page 3 sub-page address control is described in PFSM.
(3) The content stored in address 0xF0 through 0xF9 is related to the register CRC and is described in Updating the Register CRC.
(4) Page 1 registers 0x00, 0x02, 0x0B, 0x15, 0xA8, 0xB1, 0xBA, and 0xC3 are not to be changed from the factory settings.
(5) Page 1 register 0x41 is described in Section 5.4