SLVUBI2A July   2018  – October 2020 TPS650330-Q1 , TPS650331-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Requirements
  4. 3 Operation Instructions
    1. 3.1 Configuring the USB to I2C Adapter
    2. 3.2 Regulator Input Supplies and Features
      1. 3.2.1 Buck 1 Input Supply
      2. 3.2.2 Mid-Vin Buck1 Features
      3. 3.2.3 Buck 2 Input Supply
      4. 3.2.4 Buck 3 Input Supply
      5. 3.2.5 Low-Vin Buck2 and Buck3 Features
      6. 3.2.6 LDO Input Supply
      7. 3.2.7 Low Noise LDO Features
    3. 3.3 Selecting the Logic Supply Voltage
  5. 4 EVM Configurations
  6. 5 Test Points
    1. 5.1 Voltage Test Points
  7. 6 Graphical User Interface
    1. 6.1 TPS650330-Q1 EVM Debugging
      1. 6.1.1 I2C Communication Port and Adapter Debugging
      2. 6.1.2 Updating MCU Firmware
    2. 6.2 Navigating the GUI
      1. 6.2.1 Home
      2. 6.2.2 Block Diagram
      3. 6.2.3 Registers
      4. 6.2.4 Device Configuration
        1. 6.2.4.1 Using Device Configuration to Define Spin Settings
        2. 6.2.4.2 Configuring the Power Sequence
      5. 6.2.5 Re-Program PMIC
    3. 6.3 In-Circuit Programming
  8. 7 Typical Performance Plots
    1. 7.1 Power Sequence Plots
    2. 7.2 Load Transient Plots
    3. 7.3 Output Voltage Ripple Plots
    4. 7.4 Efficiency Plots
    5. 7.5 LDO Output Noise
  9. 8 TPS650330-Q1 EVM Schematic
  10. 9 TPS650330-Q1 EVM PCB Layers
  11. 10TPS650330-Q1 EVM Bill of Materials
  12. 11TPS650330-Q1 Silicon Revision Changes
  13. 12Revision History

11 TPS650330-Q1 Silicon Revision Changes

The final silicon revision for the TPS65033x-Q1 family of PMICs is denoted B0. This corresponds to die revision PG 2.0. Table 11-1 lists the feature changes compared to the first revision of silicon, A0 or PG 1.0.

Table 11-1 TPS65033x-Q1 Silicon Revision B0 Feature Changes
Item Design Block Parameter Impacted Silicon Revision A0 Silicon Revision B0 Details
1 BUCK1 Output Voltage Settings 3.0 V to 4.0 V 2.5 V to 4.0 V Maintains 50 mV increments
2 LDO Output Voltage Settings 2.7 V to 3.3 V 1.8 V, 2.5 V to 3.3 V 1.8 V and 1.825 V settings 2.5 V to 3.2 V settings in 25 mV increments 3.3 V setting
3 BUCK1 PVIN_B1_UVLO Rising threshold only Rising and Falling thresholds Same threshold settings as Rising thesholds with a 4% hysteresis delta betweein rising and falling
4 Digital Warm Threshold Exceeding Warm Threshold will keep State Machine from transitioning to the Active state Option to allow the State Machine to transition to the Active State if the Warm Threshold is exceeded User programmable in pre-production devices.Factory programmable in production devices.
5 Digital LDO Pre-Bias Condition Not applicable Option to allow the LDO to power on into a pre-bias condition User programmable in pre-production devices.Factory programmable in production devices.
6 Digital I2C Bus Always enabled Option to disable Factory programmable only
7 Digital Configuration CRC Can be disabled by the user during the configuration process Can be disabled by the user during the configuration process and programmed to remain disabled User programmable in pre-production devices.Factory programmable in production devices.
8 Digital State Transition Control Not applicable Option to define the state transition for Priority 2 Faults (either the Reset State or Wait Power Cycle State) User programmable in pre-production devices.Factory programmable in production devices.Does not apply to the TPS650331-Q1 device.
9 Digital ABIST Run Time Control ABIST only runs on power up ABIST runs on power up or whenever commanded to run Option is factory programmable only
10 Digital SEQ Pin Latch Not applicable Option to latch the state of the SEQ pin in order to perform a complete power up or power down sequence Option is factory programmable only
11 Digital Power Good Status Register Not applicable Register bits added to provide the power good status of BUCK1, BUCK2, BUCK3, and the LDO. Status bits also added for nRSTOUT, GPIO, and SEQ pins Read only register