SLVUC46D March   2021  – November 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
      1. 1.1.1 Purpose and Scope
  5. 2Evaluation Hardware Overview
    1. 2.1 Connections Overview
    2. 2.2 Connection Details
      1. 2.2.1 Common Connectors and Headers Across all EVM Variants
      2. 2.2.2 MCU Reset and User Button
      3. 2.2.3 Communication Interfaces
      4. 2.2.4 Supply Input
      5. 2.2.5 Current Limit Header (RIPROPI)
      6. 2.2.6 Device Signal and Control Header
      7. 2.2.7 Device Signal Test Points
    3. 2.3 LED Indicators
    4. 2.4 Headers and Connectors (Hardware Device Variant)
    5. 2.5 Headers and Connectors (SPI variant)
  6. 3EVM GUI Control Application
    1. 3.1 MSP430 FET Drivers
    2. 3.2 Cloud-based GUI
    3. 3.3 Local Installation
  7. 4EVM GUI Operation
    1. 4.1 Hardware Setup
    2. 4.2 Launching the DRV824x_DRV814x-Q1EVM GUI Application
    3. 4.3 Using the DRV824x_DRV814x-Q1EVM GUI Application
      1. 4.3.1 Register Map Page (SPI Device Variant)
      2. 4.3.2 Driver Control Page (SPI Device Variant)
      3. 4.3.3 Driver Control Page (HW Device Variant)
      4. 4.3.4 Updating Firmware
  8. 5Revision History

Overview

The DRV824x and DRV814x family of devices are a fully integrated H-bridge and half-bridge drivers, respectively, intended for a wide range of automotive applications. The DRV824x device can be configured as a single H-bridge driver, or two independent half-bridge drivers. Designed in Texas Instruments' proprietary high power BiCMOS process technology node, this monolithic die device in a power package offers excellent power handling and thermal capability while providing compact package size, ease of layout, EMI control, accurate current sense, robustness and diagnostic capability. The DRV824x and DRV814x family of devices each has an identical pin function with scalable RDSON (current capability) to support different loads with minimal design changes within their respective family (H-bridge or half-bridge).

The device integrates an N-channel output stage, charge pump regulator, high side current sensing and regulation, current proportional output, and protection circuitry. A low-power sleep mode is provided to achieve ultra-low quiescent current draw by shutting down most of the internal circuitry. The device offers voltage monitoring and load diagnostics as well as protection features against output over current and device over temperature. Fault conditions are indicated on the nFAULT pin. The device is available in two interface variants - hardware (“HW”) and SPI. The HW variant uses strapping resistors for fixed configuration. The SPI variant offers more flexibility in device configuration and fault observability with an external controller.