SNLA224A June   2014  – January 2024 DS90UB913A-Q1 , DS90UB954-Q1 , DS90UB960-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Theory of Operation for Power Over Coax
    1. 2.1 Inductor Characteristics
    2. 2.2 Capacitor Characteristics
    3. 2.3 Ferrite Bead Characteristics
  6. 3Design Considerations
    1. 3.1 Frequency Range
    2. 3.2 Power Considerations
    3. 3.3 Inductor Size Considerations
    4. 3.4 Layout Considerations
  7. 4FPD-Link PoC Requirements
    1. 4.1 Channel Requirements
    2. 4.2 PoC Noise Requirements
      1. 4.2.1 VPoC Noise and Pulse
      2. 4.2.2 RIN+ Noise
      3. 4.2.3 Causes of PoC Noise
      4. 4.2.4 Noise Measurement Best Practices
      5. 4.2.5 Reducing Effects of PoC Noise
  8. 5TI Recommended PoC Networks
    1. 5.1 PoC Network From FPD-Link III Data Sheet
    2. 5.2 Murata Networks
      1. 5.2.1 Murata Network 1
      2. 5.2.2 Murata Network 2
      3. 5.2.3 Murata Network 3
    3. 5.3 TDK Networks
      1. 5.3.1 TDK Network 1
      2. 5.3.2 TDK Network 2
      3. 5.3.3 TDK Network 3
      4. 5.3.4 TDK Network 4
      5. 5.3.5 TDK Network 5
      6. 5.3.6 TDK Network 6
      7. 5.3.7 TDK Network 7
      8. 5.3.8 TDK Network 8
    4. 5.4 Coilcraft Networks
      1. 5.4.1 Coilcraft Network 1
      2. 5.4.2 Coilcraft Network 2
      3. 5.4.3 Coilcraft Network 3
      4. 5.4.4 Coilcraft Network 4
  9. 6Summary
  10. 7References
  11. 8Revision History

4.2 PoC Noise Requirements

PoC networks must be designed with the integrity of the high-speed signal in mind. The network cannot interfere with data transmission, and the DC signal must have as little noise as possible. Noise seen on the PoC voltage supply and the deserializer RIN+ pin are particularly important and must remain below the recommended conditions. Figure 4-1 shows the measurement nodes of the VPoC and RIN+ noise relative to the system.

GUID-20230712-SS0I-JMSV-BLVV-6JTCCNMS3BCX-low.svg Figure 4-1 PoC Noise Measurement Nodes