SNLA224A June   2014  – January 2024 DS90UB913A-Q1 , DS90UB954-Q1 , DS90UB960-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Theory of Operation for Power Over Coax
    1. 2.1 Inductor Characteristics
    2. 2.2 Capacitor Characteristics
    3. 2.3 Ferrite Bead Characteristics
  6. 3Design Considerations
    1. 3.1 Frequency Range
    2. 3.2 Power Considerations
    3. 3.3 Inductor Size Considerations
    4. 3.4 Layout Considerations
  7. 4FPD-Link PoC Requirements
    1. 4.1 Channel Requirements
    2. 4.2 PoC Noise Requirements
      1. 4.2.1 VPoC Noise and Pulse
      2. 4.2.2 RIN+ Noise
      3. 4.2.3 Causes of PoC Noise
      4. 4.2.4 Noise Measurement Best Practices
      5. 4.2.5 Reducing Effects of PoC Noise
  8. 5TI Recommended PoC Networks
    1. 5.1 PoC Network From FPD-Link III Data Sheet
    2. 5.2 Murata Networks
      1. 5.2.1 Murata Network 1
      2. 5.2.2 Murata Network 2
      3. 5.2.3 Murata Network 3
    3. 5.3 TDK Networks
      1. 5.3.1 TDK Network 1
      2. 5.3.2 TDK Network 2
      3. 5.3.3 TDK Network 3
      4. 5.3.4 TDK Network 4
      5. 5.3.5 TDK Network 5
      6. 5.3.6 TDK Network 6
      7. 5.3.7 TDK Network 7
      8. 5.3.8 TDK Network 8
    4. 5.4 Coilcraft Networks
      1. 5.4.1 Coilcraft Network 1
      2. 5.4.2 Coilcraft Network 2
      3. 5.4.3 Coilcraft Network 3
      4. 5.4.4 Coilcraft Network 4
  9. 6Summary
  10. 7References
  11. 8Revision History

3.4 Layout Considerations

The layout of the PoC network is equally important as the network design. Due to the PoC network components making direct contact with the high-speed signal trace, good layout techniques and component placement are crucial to maintain signal integrity and remain within the insertion loss and return loss requirements. Both the high-speed channel and PoC network require tightly controlled 50-Ohms (+/-10%) impedance to minimize reflections. In addition to impedance, the PCB traces need to be thick enough to support the maximum expected current load.

Place the first inductive component of the PoC network orthogonally to be barely touching the high-speed RIN+ trace. An anti-pad must be added under the first component to keep the impedance as close to 50-Ohms as possible. The anti-pad is created by adding a cut-out to the ground plane directly underneath the component’s landing pad. Since a continuous ground reference is required for the high-speed and PoC traces, the cut-out must not include any area under the connecting trace. Place the remaining PoC components close together to minimize the total footprint of the PoC network and limit 90-degree routing. For best EMI performance, do not route any high-frequency signals, including the PoC network, near the edge of the PCB board. Figure 3-1 shows an example PoC PCB layout with many of the previously described recommendations highlighted.

GUID-C88F229D-8862-40B0-B771-9DE5BA75593A-low.gif Figure 3-1 Example PoC Layout and Routing

Keeping the entire PoC network on the same layer as the high-speed RIN+ trace is recommended since vias can result in impedance discontinuities. However, if space constraints arise, all components other than the first inductive component can be routed to a layer other than the layer with the high-speed trace. To maintain the 50-Ohm impedance, add ground reference vias near all signal vias. When sending signals between layers, care needs to be taken to avoid creating stubs. A stub is any transmission line that is only connected at one end. Stubs are commonly created by vias, routing, or through-hole connectors, which create reflections and degrade the signal quality.

For additional recommendations, refer to device data sheets.