SNLU269 april 2023 SN75LVPE3410
Table 5-1 lists the Channel registers. All register offset addresses not listed in Table 5-1 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | reg_00 | Go | |
0x1 | reg_01 | Go | |
0x3 | reg_03 | Go | |
0x4 | reg_04 | Go | |
0x6 | reg_06 | Go | |
0xD | reg_0D | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
reg_00 is shown in Table 5-3.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 - 3 | RESERVED | R/W | 1b00000 |
Reserved |
2 | rst_regs | R/W | 1b0 |
Channel Reset Control: |
1 - 0 | RESERVED | R/W | 1b00 |
Reserved |
reg_01 is shown in Table 5-4.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | rx_det_comp_p | R | 1b0 |
Rx Detect Positive Polarity Status: |
6 | rx_det_comp_n | R | 1b0 |
Rx Detect Negative Polarity Status: |
5 - 0 | RESERVED | R | 1b000000 |
Reserved |
reg_03 is shown in Table 5-5.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | eq_bw_1 | R/W | 1b1 |
CTLE Bandwidth Control: |
6 | eq_bw_0 | R/W | 1b0 |
See MSB |
5 | eq_bst2_2 | R/W | 1b0 |
CTLE Boost Stage 2 Control. |
4 | eq_bst2_1 | R/W | 1b0 |
See MSB |
3 | eq_bst2_0 | R/W | 1b0 |
See MSB |
2 | eq_bst1_2 | R/W | 1b0 |
CTLE Boost Stage 1 Control. |
1 | eq_bst1_1 | R/W | 1b0 |
See MSB |
0 | eq_bst1_0 | R/W | 1b0 |
See MSB |
reg_04 is shown in Table 5-6.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 |
Reserved |
6 | eq_term_en | R/W | 1b0 |
Enable CTLE Termination |
5 | eq_hi_gain | R/W | 1b0 |
Set CTLE DC Gain: |
4 | eq_en_dc_off | R/W | 1b1 |
Enable CTLE DC Offset Correction: |
3 | eq_en | R/W | 1b0 |
Enable CTLE |
2 - 1 | RESERVED | R/W | 1b11 |
Reserved |
0 | eq_en_bypass | R/W | 1b0 |
Enable CTLE Stage 1 Bypass: |
reg_06 is shown in Table 5-7.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | drv_sel_vod_1 | R/W | 1b1 |
TX VOD Select: |
6 | drv_sel_vod_0 | R/W | 1b1 |
See MSB |
5 | drv_eq_en_override | R/W | 1b0 |
Enable overrides for driver and equalizer enables. |
4 | drv_en_pre | R/W | 1b0 |
Enable Pre-driver. |
3 | drv_en | R/W | 1b0 |
Enable Driver. |
2 | drv_en_cm_loop | R/W | 1b0 |
Enable CM Loop. |
1 - 0 | RESERVED | R/W | 1b00 |
Reserved |
reg_0D is shown in Table 5-8.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 |
Reserved |
6 | mr_rx_det_man | R/W | 1b0 |
Manual override of rx_detect_p/n decision to always return valid. |
5 | en_rx_det_count | R/W | 1b0 |
Enable RX detect valid counter |
4 | sel_rx_det_count | R/W | 1b0 |
Select valid RX detect count before enable |
3 | mr_rx_det_rst | R/W | 1b0 |
RX Detect state machine reset |
2 - 0 | RESERVED | R/W | 1b000 |
Reserved |