SNLU269 april 2023 SN75LVPE3410
There are two share registers for the SN75LVPE3410 channel control:
Register 0xFC is used to select which channel register sets are later written to. To select a channel register set, write a 1 to its corresponding bit in this global register. Note that more than one channel may be written to by setting multiple bits in register 0xFC. When performing an SMBus read transaction, however, only one channel can be selected at a time. If multiple channels are selected when attempting to perform an SMBus read, the device will return 0xFF. This functionality is important to note when using read-modify-write transactions.
Global Register | Bit | Description |
---|---|---|
0xFC | 7 | Reserved |
6 | Reserved | |
5 | Reserved | |
4 | Reserved | |
3 | Select register set for channel 3. | |
2 | Select register set for channel 2. | |
1 | Select register set for channel 1. | |
0 | Select register set for channel 0. |
Register 0xFF bit 0 is used to select the Channel Register Page for the channels selected in Register 0xFC.
Global Register | Bit | Description |
---|---|---|
0xFF | 7:2 | Reserved |
1 | 1: Broadcast write to all channels, 0xFF [0] must be set to 1. Select a single channel in 0xFC. 0: Normal operation, select channel register as defined in 0xFC. | |
0 | 1: Select Channel Registers. 0: Deselect Channel Registers. Select Share Register Page. |