SNLU269 april 2023 SN75LVPE3410
Table 4-1 lists the Share registers. All register offset addresses not listed in Table 4-1 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x4 | General_1 | Go | |
0xB | EE_Status | Go | |
0xF1 | Full_Device_ID | Go | |
0xFC | Channel_Control_1 | Go | |
0xFF | Channel_Control_2 | Go |
Complex bit access types are encoded to fit into small table cells. Table 4-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
WSC | WSC | Write / Self-Clearing |
Reset or Default Value | ||
-n | Value after reset or the default value |
General_2 is shown in Table 4-3.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 1b0 | Reserved |
6 | rst_i2c_regs | R/W | 1b0 | Device Reset Control: |
5 | rst_i2c_mas | R/WSC | 1b0 | Reset I2C master (self-clearing). |
4 - 0 | RESERVED | R/W | 1b0001 | Reserved |
EE_Status is shown in Table 4-4.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | eecfg_cmplt | R | 1b0 | EEPROM Load Status: |
6 | eecfg_fail | R | 1b0 | |
5 | eecfg_atmpt_5 | R | 1b0 | Number of attempts made to load EEPROM image. |
4 | eecfg_atmpt_4 | R | 1b0 | |
3 | eecfg_atmpt_3 | R | 1b0 | |
2 | eecfg_atmpt_2 | R | 1b0 | |
1 | eecfg_atmpt_1 | R | 1b0 | |
0 | eecfg_atmpt_0 | R | 1b0 |
Full_Device_ID is shown in Table 4-5.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DEVICE_ID_7 | R | 1b0 | Device ID: |
6 | DEVICE_ID_6 | R | 1b0 | |
5 | DEVICE_ID_5 | R | 1b1 | |
4 | DEVICE_ID_4 | R | 1b0 | |
3 | DEVICE_ID_3 | R | 1b0 | |
2 | DEVICE_ID_2 | R | 1b1 | |
1 | DEVICE_ID_1 | R | 1b1 | |
0 | DEVICE_ID_0 | R | 1b0 |
Channel_Control_1 is shown in Table 4-6.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 - 4 | RESERVED | R/W | 1b0000 | Reserved |
3 | en_q0c3 | R/W | 1b0 | Enable Channel 3 register access |
2 | en_q0c2 | R/W | 1b0 | Enable Channel 2 register access |
1 | en_q0c2 | R/W | 1b0 | Enable Channel 1 register access |
0 | en_q0c2 | R/W | 1b0 | Enable Channel 0 register access |
Channel_Control_2 is shown in Table 4-7.
Return to the Summary Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 - 2 | RESERVED | R/W | 1b0000000 | Reserved |
1 | write_all_ch | R/W | 1b0 | Enable Broadcast Write: 0: Broadcast write disabled 1: Broadcast write enabled Set en_ch_SMB (Reg 0xFF[0]) = 1 to use this function. Otherwise, the write_all_ch bit is invalid. Read-back will only occur based on the selected channel register page in Reg 0xFC. |
0 | en_ch_SMB | R/W | 1b0 | Register Access Control: |