SNOAA82 November   2021 TLV3601 , TLV3601-Q1 , TLV3603 , TLV3603-Q1


  1.   Design Process
    1.     Design Steps
    2.     Transient Simulation Results
  2.   Design References
  3.   Design Featured Comparator
  4.   Design Alternate Comparator

Design Steps

Complete Design Circuit

Step 1: LVDS Generation Using the TLV3604

The TLV3604 non-inverting input is driven by a 100-mV, 3-ns pulse with a 2.5-V DC offset (VPULSE).

LVDS Generation Using the TLV3604

Step 2: LVDS to Single-Ended Output Conversion Using the TLV3601

The LVDS outputs of the TLV3604 (LVDS_H and LVDS_L) are used to drive the inputs of the TLV3601. Since the outputs of the TLV3604 are terminated with a 100-Ω load, the voltage across this load can differentially drive the input of the TLV3601.

Connecting the TLV3601

Step 3: Configuring the GaN FET Driver

The LMG1020 enable pin (INM in the TINA simulation model) is active low and thus can be left grounded to keep the LMG1020 enabled. The series resistances on the outputs follow the LMG1020 5-V, 7-A, 5-A Low-Side GaN and MOSFET Driver For 1-ns Pulse Width Applications data sheet recommended minimum value of 2 Ω in the Typical Applications section. The shorted outputs then drive the gate of the EPC2019 GaN FET (V_GATE). The LMG1020 input is driven by the output of the TLV3601 (TLV3601_OUT).

LMG1020 Configuration

Step 4: Connecting the EPC2019 GaN FET

The GaN FET controls the 10-V supply current through the 1-Ω load. As a safety feature, a Schottky diode was placed in parallel with the load to ensure that the voltage across the load does not exceed 20 V.

Low-Side GaN FET Connections