3.4 Clocking
Make sure your input clock/crystal meets the data sheet requirements. For example:
Frequency
ESR for crystal
Load capacitance meets both the crystal’s and processor’s requirements
Crystal and caps placed physically close to processor
Double check proper voltage level for clock (for more information, see the device-specific data sheet)
Available clock sources to generate SYSCLK
CLK_SEL pin = low: RTC oscillator @ 32.768 KHz
CLK_SEL pin = high: CLKIN pin supplied by 11.2896, 12, or 12.288 MHz clock (for bootloader)
On-chip PLL and clock dividers available to modify SYSCLK frequency
Do not need RTC oscillator if...
Do not need RTC clock
Not sourcing SYSCLK from RTC oscillator
Do not need RTC-only mode
See If RTC is not used
Do not use CLKOUT as MCLK for any device such as a CODEC
CLKOUT for debugging purposes only
CLKOUT contains clock jitter, not glitch-free
Avoid using SYSCLK as the clock source for peripheral clocks that require low-jitter and high precision
For example, I2S ports should be slaved and clocked by an audio quality clock generator for high audio quality
PLL jitter depends on the PLLIN and PLLOUT frequencies - 200ps cycle-cycle is a reasonable estimate at PLLOUT (before dividers)