If CVDD supplied by DSP_LDOO (DSP_LDO_EN = low), then internal Power-on-Reset (POR) releases reset when when the DSP_LDOO voltage is above a minimum threshold voltage provided by the bandgap
If not using DSP_LDO (DSP_LDO_EN = high), implement an external power monitor to release reset when CVDD > 0.998 V (consider tolerances to guarantee CVDD > 0.998 V)
Cannot combine external CVDD supply with on-chip powergood voltage monitor - reset must be asserted externally
Always place external pull-up resistor on RESET - 100K
Nice to have push-button to reset device for debugging
A useful tip is to place a 0.1 μF cap near the reset pin to help avoid ESD-induced resets.