SPRAD85 March   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
    1. 1.1 Before Getting Started
    2. 1.2 Device (Processor) Selection
    3. 1.3 Technical Documentation
    4. 1.4 Design Documentation
  4. 2 System Block Diagram
    1. 2.1 Creating the System Block Diagram
    2. 2.2 Selecting the Boot Mode
    3. 2.3 Confirming Pin Multiplexing Compatibility
  5. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 Internal LDOs for I/O groups
      4. 3.2.4 Dual-Voltage LVCMOS I/Os
      5. 3.2.5 Dual-Voltage Dynamic Switching I/Os for SDIO
      6. 3.2.6 VPP (eFuse ROM programming supply)
    3. 3.3 Determining System Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 Note on PDN target impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  6. 4 Clocking
    1. 4.1 System Clock Inputs
    2. 4.2 Unused Clock Inputs
    3. 4.3 Clock Output
    4. 4.4 Single-Ended Clock Sources
    5. 4.5 Crystal Selection
  7. 5 JTAG
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
      2. 5.1.2 System Implementation of JTAG / Emulation
      3. 5.1.3 JTAG Termination
  8. 6 Device Configurations and Initialization
    1. 6.1 Device Reset
    2. 6.2 Latching of the Boot Modes
    3. 6.3 Watchdog Timer
  9. 7 Peripherals
    1. 7.1  Selecting Peripherals Across Functional Domains
    2. 7.2  Memory
      1. 7.2.1 Processor DDR Subsystem and Device Register Configuration
    3. 7.3  Media and Data Storage Interfaces
    4. 7.4  Ethernet Interface Using CPSW3G Common Platform Switch 3-port Gigabit Ethernet
    5. 7.5  Programmable Real-Time Unit Subsystem (PRUSS)
    6. 7.6  Universal Serial Bus (USB) Subsystem
    7. 7.7  General Connectivity
    8. 7.8  Display Subsystem (DSS)
    9. 7.9  Camera Subsystem (CSI)
    10. 7.10 Termination of Unused Peripherals and I/Os
      1. 7.10.1 EXTINTn
  10. 8 I/O Buffers and Termination
  11. 9 Power Consumption and Thermal Solutions
    1. 9.1 Power Consumption
    2. 9.2 Power Savings Modes
    3. 9.3 Guidance on Thermal Solution
  12. 10Schematics Recommendations
    1. 10.1 Selection of Component and Component Values
    2. 10.2 Schematics Development
    3. 10.3 Reviewing the Schematics
    4. 10.4 Floor Planning of the PCB
  13. 11Layout and Routing Guidelines
    1. 11.1 Escape Routing Guidelines
    2. 11.2 LPDDR4 Board Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidance
  14. 12Device Handling and Assembly
  15. 13References
  16. 14Acronyms Used in This Document

8 I/O Buffers and Termination

An important step in the hardware design, before beginning schematic capture, is to confirm both DC and AC electrical compatibility between the processor and attached external devices.

  • The device-specific data sheet has important information with regards to timing and electrical characteristics.
  • For high-speed interfaces, run IBIS simulations using IBIS models provided for the processor to confirm signal integrity.

For more information on terminations, see the General Termination Details section in the Hardware Design Guide for KeyStone II Devices.