SPRADA9 December   2023 AM62P , AM62P-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor Selection
    3. 1.3 Technical Documentation
    4. 1.4 Design Documentation
  5. 2 Block Diagram
    1. 2.1 Constructing the Block Diagram
    2. 2.2 Selecting the Boot Mode
    3. 2.3 Confirming Pinmux (Pin Multiplexing Capability)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power
      2. 3.1.2 Discrete Power
    2. 3.2 Power (Supply) Rails
      1. 3.2.1 Core Supply
      2. 3.2.2 Peripheral Power Supply
      3. 3.2.3 Internal LDOs for IO Groups (Processor IO Groups)
      4. 3.2.4 Dual-Voltage IOs (Processor IOs)
      5. 3.2.5 Dual-Voltage Dynamic Switching IOs
      6. 3.2.6 VPP (eFuse ROM Programming Supply)
    3. 3.3 Determining Board Power Requirements
    4. 3.4 Power Supply Filters
    5. 3.5 Power Supply Decoupling and Bulk Capacitors
      1. 3.5.1 Note on PDN Target Impedance
    6. 3.6 Power Supply Sequencing
    7. 3.7 Supply Diagnostics
    8. 3.8 Power Supply Monitoring
  7. 4 Clocking
    1. 4.1 Processor External Clock Inputs
      1. 4.1.1 Unused WKUP_LFOSC0
      2. 4.1.2 LVCMOS Digital Clock Source
      3. 4.1.3 Crystal Selection
    2. 4.2 Processor Clock Outputs
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection of JTAG Interface Signals
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Boot Mode Configuration
    3. 6.3 Resetting the Attached Devices
    4. 6.4 Watchdog Timer
  10. 7 Processor Peripherals
    1. 7.1  Selecting Peripherals Across Domains
    2. 7.2  Memory (DDRSS)
      1. 7.2.1 Processor DDR Subsystem and Device Register Configuration
      2. 7.2.2 Calibration Resistor Connection
    3. 7.3  Media and Data Storage Interfaces
    4. 7.4  Ethernet Interface Using Common Platform Ethernet Switch 3-port Gigabit (CPSW3G)
    5. 7.5  Programmable Real-Time Unit Subsystem (PRUSS)
    6. 7.6  Universal Serial Bus (USB) Subsystem
    7. 7.7  General Connectivity Peripherals
    8. 7.8  Display Subsystem (DSS)
    9. 7.9  Camera Subsystem (CSI)
    10. 7.10 Connection of Processor Power Pins, Unused Peripherals and IOs
      1. 7.10.1 External Interrupt (EXTINTn)
      2. 7.10.2 Reserved Pins (Signals)
  11. 8 Interfacing of Processor IOs ( LVCMOS or Open-Drain or Fail-Safe Type IO Buffers) and Simulations
  12. 9 Power Consumption and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current for Different Supply Rails
    3. 9.3 Power Modes
    4. 9.4 Thermal Design Guidelines
  13. 10Schematic Design, Capture and Review
    1. 10.1 Selection of Components and Values
    2. 10.2 Schematic Design and Capture
    3. 10.3 Schematics Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 LPDDR4 Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Board Layer Count and Stack-up
      1. 11.4.1 Simulation Recommendations
    5. 11.5 Reference for Steps to be Followed for Running Simulation
  15. 12Device Handling and Assembly
    1. 12.1 Soldering Recommendations
      1. 12.1.1 Additional References
  16. 13References
    1. 13.1 Processor Specific
    2. 13.2 Common
  17. 14Terminology
  18. 15Revision History

7.7 General Connectivity Peripherals

The processor supports multiple instances of UART, Serial Peripheral Interface (SPI-MCSPI), I2C, Multichannel Audio Serial Port (MCASP), Enhanced Pulse Width Modulator (EPWM), Enhanced Quadrature Encoder Pulse (EQEP), ECAP, CAN with CAN-FD support and GPIO modules.

For I2C interfaces with open-drain output type buffer (MCU_I2C0 and WKUP_I2C0), an external pullup is recommended irrespective of peripheral usage and IO configuration. Refer Pin Connectivity Requirements section of device-specific data sheet.

When MCU_I2C0 and WKUP_I2C0 are pulled to 3.3 V supply, the inputs have slew rate limit requirements. An RC is recommended to limit the slew rate.

An external pullup is recommended for the I2C interfaces (I2C0..3) with LVCMOS IOs emulated open-drain outputs. For the available LVCMOS IOs with emulated open-drain output I2C instances, refer the device-specific data sheet.

For more information, see the [FAQ] AM62P / AM62P-Q1 Custom board hardware design – I2C interface.

The number of peripheral instances available depends on the processor selection. The required interfaces can be configured using the SysConfig-PinMux tool based on the application.

For more details, refer the Peripherals chapter of the device-specific TRM.