SPRADA9 December 2023 AM62P , AM62P-Q1
DDR Subsystem currently supports LPDDR4 memory interface. Refer Memory Subsystem, DDR Subsystem (DDRSS) section in the Features chapter of device-specific data sheet for data bus width, inline ECC support, speed and max addressable range selection.
The allowed memory configurations are 1 X 32-bit or 1 X 16-bit.
1 X 8-bit memory configuration is not a valid configuration.
Based on the application requirements, same memory (LPDDR4) device can be used with the AM625 / AM623 / AM625-Q1 / AM620-Q1 , AM62A7 / AM62A3 and AM62P / AM62P-Q1 processors due to the availability of 1 X 16-bit configuration.
When the AM62P / AM62P-Q1 processors are configured for 16-bit configuration, follow the DQS2..3 and other unused signal connection recommendations shown in the 16-Bit, Single Rank LPDDR4 Implementation example of the AM62Ax / AM62Px LPDDR4 Board Design and Layout Guidelines.
Refer Pin Connectivity Requirements section of the device-specific data sheet for connecting the DDRSS signals when not used.
For more details, refer the DDR Subsystem (DDRSS) section in the Memory Controllers chapter of the device-specific TRM.