SPRADG5 January   2024 DRA821U , DRA821U-Q1 , TDA4AL-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UART Introduction
    1. 1.1 Jacinto 7 UART Overview
    2. 1.2 Jacinto 7 UART Features
    3. 1.3 Jacinto 7 UART Functional Introduction
  5. 2UART Usage Overview
    1. 2.1 WKUP_UART0 Usage
    2. 2.2 MCU_UART0 Usage
    3. 2.3 MAIN_UARTx Usage
  6. 3Log Level Design on Software Module
  7. 4Change UART Instance
    1. 4.1 Change MAIN_UARTx for MAIN Domain
    2. 4.2 Set Standalone UART Port for DSP/MCU
  8. 5Summary
  9. 6References

Set Standalone UART Port for DSP/MCU

By default, the MCU and DSP cores of J7 SOC do not set a separate UART for serial port output. For TDA4X, by default the log of every core except A72 cores will be written to a shared memory, and then the A72 application will read it and print these logs to MAIN_UARTX serial port. However, in order to facilitate debugging, it is often necessary to print logs of multiple cores at the same time or to continue to print logs when core A is not working properly. In this case, it is necessary to configure a separate serial port for the MCU/DSP cores. The following uses TDA4VM as an example to set up a separate serial port for C7.

  1. Add UART Initial configuration in MAIN function.
    diff --git a/vision_apps/platform/j721e/rtos/c7x_1/main.c 
    b/vision_apps/platform/j721e/rtos/c7x_1/main.c
    index 0dcfa4fd..e857838b 100755
    --- a/vision_apps/platform/j721e/rtos/c7x_1/main.c
    +++ b/vision_apps/platform/j721e/rtos/c7x_1/main.c
    @@ -88,7 +88,8 @@
    #include <ti/sysbios/family/c7x/Hwi.h>
    #include <ti/sysbios/family/c7x/Mmu.h>
    #endif
    +#include <ti/drv/uart/UART.h>
    +#include <ti/drv/uart/UART_stdio.h>
    /* For J7ES/J721E/TDA4VM the upper 2GB DDR starts from 0x0008_8000_0000 */
    /* This address is mapped to a virtual address of 0x0001_0000_0000 */
    #define DDR_C7X_1_LOCAL_HEAP_VADDR (DDR_C7X_1_LOCAL_HEAP_ADDR)
    @@ -96,18 +97,33 @@
    +extern int uart_print_test(void);
    +extern int uart_test(void);
    @@ -181,9 +197,13 @@ int main(void)
    {
    TaskP_Params tskParams;
    TaskP_Handle task;
    OS_init();
    +/* Set TDA4VM PINMUX UART2_RX(PIN Y1)&UART2_TX(PIN Y5)
    +*  We can get the register address from the datasheet
    +*/
    + *((int *)(0x00011C1DC))=0x50003;
    + *((int *)(0x00011C1E0))=0x10003;
    + uart_print_test();
    appC7xClecInitDru();
  2. Create UART instance for C7.

    Create c7_uart_print temp folder under the path vision_apps/basic_demos/ and create c7_uart_print.c and concerto.mk file as initial configuration UART library.

    The following content is for c7_uart_print.c.

    #include <ti/drv/uart/UART.h>
    #include <ti/drv/uart/UART_stdio.h>
    #include <ti/board/src/j721e_evm/include/board_utils.h>
    #include <ti/board/board.h>
    #include <ti/board/src/j721e_evm/include/board_cfg.h>
    int uart_test(void)
    {
       UART_printf("\n=============================================\n");
       UART_printf("\n**********c7x uart printf********************\n"); 
       UART_printf("*                 UART Test                 *\n");
       UART_printf("*********************************************\n");
       return 0;
    }
    
    int uart_print_test(void)
    {
        Board_initParams_t initParams;
    
        /* Verify the SoC UART0 */
        Board_getInitParams(&initParams);
        initParams.uartInst = 2;
        initParams.uartSocDomain = BOARD_SOC_DOMAIN_MAIN;
        Board_setInitParams(&initParams);
        Board_init(BOARD_INIT_UART_STDIO);
    
        uart_test();
       
    return 0;
    }

    The following content is for concerto.mk.

    ifeq ($(TARGET_CPU),$(filter $(TARGET_CPU), x86_64 C71 C7120))
    
    include $(PRELUDE)
    TARGET      := c7_uart_print
    TARGETTYPE  := library
    CSOURCES    := $(call all-c-files)
    CPPSOURCES  := $(call all-cpp-files)
    CFLAGS+= -mv7100 --c11
    ifeq ($(TARGET_CPU), x86_64)
    IDIRS       += $(CGT7X_ROOT)/host_emulation/include/C7100
    CFLAGS += --std=c++14 -D_HOST_EMULATION -pedantic -fPIC -w -c -g -o4
    CFLAGS += -Wno-sign-compare
    endif
    
    include $(FINALE)
    
    endif
    
  3. Change output log from shared memory to UART FIFO.
    diff --git a/vision_apps/utils/console_io/src/app_log_writer.c b/vision_apps/utils/console_io/src/app_log_writer.c
    index a02a785c..561d1434 100755
    --- a/vision_apps/utils/console_io/src/app_log_writer.c
    +++ b/vision_apps/utils/console_io/src/app_log_writer.c
    @@ -220,6 +220,32 @@ int32_t  appLogWrPutString(app_log_wr_obj_t *obj)
     
         return status;
     }
    +#if defined C71
    +int32_t  c7x_appLogWrPutString(app_log_wr_obj_t *obj)
    +{
    +    int32_t status = 0;
    +    volatile uint32_t copy_bytes,num_bytes;
    +    volatile uint8_t *buf = (uint8_t*)obj->buf;
    +
    +
    +    if (0 == status)
    +    {
    +        num_bytes = strlen((char*)buf);
    +
    +        if (num_bytes <= 0)
    +        {
    +            status = -1;
    +        }
    +    }
    +
    +    if (0 == status)
    +    {
    +        UART_puts(buf,num_bytes);
    +    }
    +
    +    return status;
    +}
    +#endif
     
     void appLogPrintf(const char *format, ...)
     {
    @@ -266,6 +292,8 @@ void appLogPrintf(const char *format, ...)
                 printf(obj->buf);
                 #endif
             }
    +        #elif defined C71
    +        c7x_appLogWrPutString(obj);
             #else
             appLogWrPutString(obj);
             #endif
  4. Add Library path for compile binary.
    diff --git a/vision_apps/platform/j721e/rtos/concerto_c7x_inc.mak b/vision_apps/platform/j721e/rtos/concerto_c7x_inc.mak
    index 4e3c5a29..4a9c94db 100755
    --- a/vision_apps/platform/j721e/rtos/concerto_c7x_inc.mak
    +++ b/vision_apps/platform/j721e/rtos/concerto_c7x_inc.mak
    @@ -19,6 +19,10 @@ endif
     ifeq ($(RTOS),SAFERTOS)
            LDIRS += $(PDK_PATH)/packages/ti/osal/lib/safertos/$(SOC)/c7x/$(TARGET_BUILD)/
     endif
    +
    +LDIRS += $(PDK_PATH)/packages/ti/drv/uart/lib/$(SOC)/c7x/$(TARGET_BUILD)/
    +LDIRS += $(PDK_PATH)/packages/ti/drv/i2c/lib/$(SOC)/c7x/$(TARGET_BUILD)/
    +LDIRS += $(PDK_PATH)/packages/ti/board/lib/$(SOC)_evm/c7x/$(TARGET_BUILD)/
     LDIRS += $(PDK_PATH)/packages/ti/csl/lib/$(SOC)/c7x/$(TARGET_BUILD)/
     LDIRS += $(PDK_PATH)/packages/ti/drv/ipc/lib/$(SOC)/c7x_1/$(TARGET_BUILD)/
     LDIRS += $(PDK_PATH)/packages/ti/drv/udma/lib/$(SOC)/c7x_1/$(TARGET_BUILD)/
    @@ -45,6 +49,7 @@ STATIC_LIBS += vx_app_ptk_demo_common
     STATIC_LIBS += vx_kernels_common
     STATIC_LIBS += vx_target_kernels_img_proc_c71
     STATIC_LIBS += vx_app_c7x_voxel2point
    +STATIC_LIBS += c7_uart_print
     
     PTK_LIBS =
     PTK_LIBS += ptk_algos
    @@ -76,6 +81,9 @@ ADDITIONAL_STATIC_LIBS += ipc.ae71
     ADDITIONAL_STATIC_LIBS += dmautils.ae71
     ADDITIONAL_STATIC_LIBS += sciclient.ae71
     ADDITIONAL_STATIC_LIBS += udma.ae71
    +ADDITIONAL_STATIC_LIBS += ti.drv.uart.ae71
    +ADDITIONAL_STATIC_LIBS += ti.board.ae71
    +ADDITIONAL_STATIC_LIBS += ti.drv.i2c.ae71
     
     ifeq ($(RTOS),FREERTOS)
            ADDITIONAL_STATIC_LIBS += ti.kernel.freertos.ae71
    

    The above describes all changes at the SDK level. The next step is only required to recompile the C7 firmware and flash it to SD card or EMMC.