Figure 1-1 shows the Jacinto 7 UART functional block diagram. When the processor needs to send data, it only needs to write the output data into the FIFO through CPU/DMA. Then, the data is automatically transmitted to TX pin by UART_THR register and converted into TTL level. The data transmission is completed if the UART_THR register is empty. During the data receiving process, the TTL level is firstly converted into bit data through the pin, and is written to the FIFO by UART_RHR. When the FIFO reaches a threshold (maximum 64 Bytes), a CPU/DMA interrupt will be triggered to write the data to the memory. When enough data is read and the data in the FIFO is lower than the threshold, the interrupt condition disappears and the data receiving is finished.

Figure 1-1 UART Functional Block Diagram