SPRUHM8K December   2013  – May 2024 F28377D-SEP , TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II)
  5. 3 System Control and Interrupt
    1. 3.1  Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Power-On Reset (POR)
      4. 3.3.4  Debugger Reset (SYSRS)
      5. 3.3.5  Watchdog Reset (WDRS)
      6. 3.3.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.3.7  DCSM Safe Code Copy Reset (SCCRESET)
      8. 3.3.8  Hibernate Reset (HIBRESET)
      9. 3.3.9  Hardware BIST Reset (HWBISTRS)
      10. 3.3.10 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable ECC Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
        4. 3.5.3.4 NMI Vector Fetch Mismatch
        5. 3.5.3.5 CPU2 Watchdog or NMI Watchdog Reset
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 Missing Clock Detection Logic
      3. 3.6.3 PLLSLIP Detection
      4. 3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check
      5. 3.6.5 NMIWDs
      6. 3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
      7. 3.6.7 ECC Enabled Flash Memory
      8. 3.6.8 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 XCLKOUT
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Clock Source and PLL Setup
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 Clock Configuration Examples
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timers
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 IDLE
      2. 3.10.2 STANDBY
      3. 3.10.3 HALT
      4. 3.10.4 Hibernate (HIB)
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1  Dedicated RAM (Dx RAM)
        2. 3.11.1.2  Local Shared RAM (LSx RAM)
        3. 3.11.1.3  Global Shared RAM (GSx RAM)
        4. 3.11.1.4  CPU Message RAM (CPU MSG RAM)
        5. 3.11.1.5  CLA Message RAM (CLA MSGRAM)
        6. 3.11.1.6  Access Arbitration
        7. 3.11.1.7  Access Protection
          1. 3.11.1.7.1 CPU Fetch Protection
          2. 3.11.1.7.2 CPU Write Protection
          3. 3.11.1.7.3 CPU Read Protection
          4. 3.11.1.7.4 CLA Fetch Protection
          5. 3.11.1.7.5 CLA Write Protection
          6. 3.11.1.7.6 CLA Read Protection
          7. 3.11.1.7.7 DMA Write Protection
        8. 3.11.1.8  Memory Error Detection, Correction and Error Handling
          1. 3.11.1.8.1 Error Detection and Correction
          2. 3.11.1.8.2 Error Handling
        9. 3.11.1.9  Application Test Hooks for Error Detection and Correction
        10. 3.11.1.10 RAM Initialization
    12. 3.12 Flash and OTP Memory
      1. 3.12.1  Features
      2. 3.12.2  Flash Tools
      3. 3.12.3  Default Flash Configuration
      4. 3.12.4  Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
      5. 3.12.5  Flash Module Controller (FMC)
      6. 3.12.6  Flash and OTP Memory Power-Down Modes and Wakeup
      7. 3.12.7  Flash and OTP Memory Performance
      8. 3.12.8  Flash Read Interface
        1. 3.12.8.1 FMC Flash Read Interface
          1. 3.12.8.1.1 Standard Read Mode
          2. 3.12.8.1.2 Prefetch Mode
            1. 3.12.8.1.2.1 Data Cache
      9. 3.12.9  Erase/Program Flash
        1. 3.12.9.1 Erase
        2. 3.12.9.2 Program
        3. 3.12.9.3 Verify
      10. 3.12.10 Error Correction Code (ECC) Protection
        1. 3.12.10.1 Single-Bit Data Error
        2. 3.12.10.2 Uncorrectable Error
        3. 3.12.10.3 SECDED Logic Correctness Check
        4. 3.12.10.4 Reading ECC Memory From a Higher Address Space
      11. 3.12.11 Reserved Locations Within Flash and OTP Memory
      12. 3.12.12 Procedure to Change the Flash Control Registers
      13. 3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
      14. 3.12.14 Flash Pump Ownership Semaphore
        1. 3.12.14.1 Clock Configuration Semaphore
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 Emulation Code Security Logic (ECSL)
        2. 3.13.1.2 CPU Secure Logic
        3. 3.13.1.3 Execute-Only Protection
        4. 3.13.1.4 Password Lock
        5. 3.13.1.5 JTAG Lock
        6. 3.13.1.6 Link Pointer and Zone Select
          1. 3.13.1.6.1 C Code Example to get Zone Select Block Addr for Zone1
        7. 3.13.1.7 Flash and OTP Memory Erase/Program
        8. 3.13.1.8 Safe Copy Code
        9. 3.13.1.9 SafeCRC
      2. 3.13.2 CSM Impact on Other On-Chip Resources
      3. 3.13.3 Incorporating Code Security in User Applications
        1. 3.13.3.1 Environments That Require Security Unlocking
        2. 3.13.3.2 CSM Password Match Flow
        3. 3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
          1. 3.13.3.3.1 C Code Example to Unsecure C28x Zone1
          2. 3.13.3.3.2 C Code Example to Resecure C28x Zone1
        4. 3.13.3.4 Environments That Require ECSL Unlocking
        5. 3.13.3.5 ECSL Password Match Flow
        6. 3.13.3.6 ECSL Disable Considerations for any Zone
          1. 3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
        7. 3.13.3.7 Device Unique ID
    14. 3.14 JTAG
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 Software
      1. 3.16.1 SYSCTL Examples
        1. 3.16.1.1 Missing clock detection (MCD)
        2. 3.16.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.16.2 TIMER Examples
        1. 3.16.2.1 CPU Timers
        2. 3.16.2.2 CPU Timers
      3. 3.16.3 MEMCFG Examples
      4. 3.16.4 INTERRUPT Examples
        1. 3.16.4.1 External Interrupts (ExternalInterrupt)
        2. 3.16.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.16.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.16.4.4 EPWM Real-Time Interrupt
      5. 3.16.5 LPM Examples
      6. 3.16.6 WATCHDOG Examples
        1. 3.16.6.1 Watchdog
    17. 3.17 System Control Registers
      1. 3.17.1  System Control Base Addresses
      2. 3.17.2  CPUTIMER_REGS Registers
      3. 3.17.3  PIE_CTRL_REGS Registers
      4. 3.17.4  WD_REGS Registers
      5. 3.17.5  NMI_INTRUPT_REGS Registers
      6. 3.17.6  XINT_REGS Registers
      7. 3.17.7  SYNC_SOC_REGS Registers
      8. 3.17.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.17.9  FLASH_PUMP_SEMAPHORE_REGS Registers
      10. 3.17.10 DEV_CFG_REGS Registers
      11. 3.17.11 CLK_CFG_REGS Registers
      12. 3.17.12 CPU_SYS_REGS Registers
      13. 3.17.13 ROM_PREFETCH_REGS Registers
      14. 3.17.14 DCSM_Z1_REGS Registers
      15. 3.17.15 DCSM_Z2_REGS Registers
      16. 3.17.16 DCSM_COMMON_REGS Registers
      17. 3.17.17 MEM_CFG_REGS Registers
      18. 3.17.18 ACCESS_PROTECTION_REGS Registers
      19. 3.17.19 MEMORY_ERROR_REGS Registers
      20. 3.17.20 ROM_WAIT_STATE_REGS Registers
      21. 3.17.21 FLASH_CTRL_REGS Registers
      22. 3.17.22 FLASH_ECC_REGS Registers
      23. 3.17.23 CPU_ID_REGS Registers
      24. 3.17.24 UID_REGS Registers
      25. 3.17.25 DCSM_Z1_OTP Registers
      26. 3.17.26 DCSM_Z2_OTP Registers
      27. 3.17.27 Register to Driverlib Function Mapping
        1. 3.17.27.1 CPUTIMER Registers to Driverlib Functions
        2. 3.17.27.2 ASYSCTL Registers to Driverlib Functions
        3. 3.17.27.3 PIE Registers to Driverlib Functions
        4. 3.17.27.4 SYSCTL Registers to Driverlib Functions
        5. 3.17.27.5 NMI Registers to Driverlib Functions
        6. 3.17.27.6 XINT Registers to Driverlib Functions
        7. 3.17.27.7 DCSM Registers to Driverlib Functions
        8. 3.17.27.8 MEMCFG Registers to Driverlib Functions
        9. 3.17.27.9 FLASH Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  Boot ROM Registers
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
    5. 4.5  Configuring Boot Mode Pins
    6. 4.6  Configuring Get Boot Options
    7. 4.7  Configuring Emulation Boot Options
    8. 4.8  Device Boot Flow Diagrams
      1. 4.8.1 Emulation Boot Flow Diagrams
      2. 4.8.2 Standalone and Hibernate Boot Flow Diagrams
    9. 4.9  Device Reset and Exception Handling
      1. 4.9.1 Reset Causes and Handling
      2. 4.9.2 Exceptions and Interrupts Handling
    10. 4.10 Boot ROM Description
      1. 4.10.1  Entry Points
      2. 4.10.2  Wait Points
      3. 4.10.3  Memory Maps
        1. 4.10.3.1 CPU1 Boot ROM Memory Map
        2. 4.10.3.2 CPU2 Boot ROM Memory Map
        3. 4.10.3.3 CLA Data ROM Memory Map
        4. 4.10.3.4 Reserved RAM and Flash Memory-Map
        5. 4.10.3.5 ROM Tables
          1. 4.10.3.5.1 Boot ROM Tables
          2. 4.10.3.5.2 CLA ROM Tables
      4. 4.10.4  Boot Modes
        1. 4.10.4.1 Wait Boot Mode
        2. 4.10.4.2 SCI Boot Mode
        3. 4.10.4.3 SPI Boot Mode
        4. 4.10.4.4 I2C Boot Mode
        5. 4.10.4.5 Parallel Boot Mode
        6. 4.10.4.6 CAN Boot Mode
        7. 4.10.4.7 USB Boot Mode
      5. 4.10.5  Boot Data Stream Structure
        1. 4.10.5.1 Bootloader Data Stream Structure
          1. 4.10.5.1.1 Data Stream Structure 8-bit
      6. 4.10.6  GPIO Assignments
      7. 4.10.7  Secure ROM Function APIs
      8. 4.10.8  Boot IPC
        1. 4.10.8.1 CPU1 IPC Commands
        2. 4.10.8.2 CPU2 IPC Commands
        3. 4.10.8.3 CPU2 IPC Error Commands
      9. 4.10.9  Clock Initializations
      10. 4.10.10 Wait State Configuration
      11. 4.10.11 Boot Status information
        1. 4.10.11.1 CPU1 Booting Status
        2. 4.10.11.2 CPU1 Boot Mode Status
        3. 4.10.11.3 CPU2 Booting Status
        4. 4.10.11.4 CPU1 IPC NAK Status
        5. 4.10.11.5 CPU2 IPC NAK Status
      12. 4.10.12 ROM Version
  7. 5 Direct Memory Access (DMA)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
    2. 5.2 Architecture
      1. 5.2.1 Common Peripheral Architecture
      2. 5.2.2 Peripheral Interrupt Event Trigger Sources
      3. 5.2.3 DMA Bus
    3. 5.3 Address Pointer and Transfer Control
    4. 5.4 Pipeline Timing and Throughput
    5. 5.5 CPU and CLA Arbitration
    6. 5.6 Channel Priority
      1. 5.6.1 Round-Robin Mode
      2. 5.6.2 Channel 1 High-Priority Mode
    7. 5.7 Overrun Detection Feature
    8. 5.8 Software
      1. 5.8.1 DMA Examples
        1. 5.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 5.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 5.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 5.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 5.9 DMA Registers
      1. 5.9.1 DMA Base Addresses
      2. 5.9.2 DMA_REGS Registers
      3. 5.9.3 DMA_CH_REGS Registers
      4. 5.9.4 DMA Registers to Driverlib Functions
  8. 6 Control Law Accelerator (CLA)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 CLA Related Collateral
      3. 6.1.3 Block Diagram
    2. 6.2 CLA Interface
      1. 6.2.1 CLA Memory
      2. 6.2.2 CLA Memory Bus
      3. 6.2.3 Shared Peripherals and EALLOW Protection
      4. 6.2.4 CLA Tasks and Interrupt Vectors
      5. 6.2.5 CLA Software Interrupt to CPU
    3. 6.3 CLA and CPU Arbitration
      1. 6.3.1 CLA Message RAM
      2. 6.3.2 CLA Program Memory
      3. 6.3.3 CLA Data Memory
      4. 6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 6.4 CLA Configuration and Debug
      1. 6.4.1 Building a CLA Application
      2. 6.4.2 Typical CLA Initialization Sequence
      3. 6.4.3 Debugging CLA Code
        1. 6.4.3.1 Breakpoint Support (MDEBUGSTOP)
      4. 6.4.4 CLA Illegal Opcode Behavior
      5. 6.4.5 Resetting the CLA
    5. 6.5 Pipeline
      1. 6.5.1 Pipeline Overview
      2. 6.5.2 CLA Pipeline Alignment
        1. 6.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       350
        3. 6.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       352
        5. 6.5.2.3 ADC Early Interrupt to CLA Response
      3. 6.5.3 Parallel Instructions
        1. 6.5.3.1 Math Operation with Parallel Load
        2. 6.5.3.2 Multiply with Parallel Add
      4. 6.5.4 CLA Task Execution Latency
    6. 6.6 Software
      1. 6.6.1 CLA Examples
        1. 6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
    7. 6.7 Instruction Set
      1. 6.7.1 Instruction Descriptions
      2. 6.7.2 Addressing Modes and Encoding
      3. 6.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 [, CNDF]
        45.       MMOV32 MRa, MRb [, CNDF]
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb[, CNDF]
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD [CNDF]
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb [, CNDF]
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 6.8 CLA Registers
      1. 6.8.1 CLA Base Addresses
      2. 6.8.2 CLA_REGS Registers
      3. 6.8.3 CLA_SOFTINT_REGS Registers
      4. 6.8.4 CLA Registers to Driverlib Functions
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Introduction
    2. 7.2 Message RAMs
    3. 7.3 IPC Flags and Interrupts
    4. 7.4 IPC Command Registers
    5. 7.5 Free-Running Counter
    6. 7.6 IPC Communication Protocol
    7. 7.7 IPC Registers
      1. 7.7.1 IPC Base Addresses
      2. 7.7.2 IPC_REGS_CPU1 Registers
      3. 7.7.3 IPC_REGS_CPU2 Registers
      4. 7.7.4 IPC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital General-Purpose I/O Control
    4. 8.4  Input Qualification
      1. 8.4.1 No Synchronization (Asynchronous Input)
      2. 8.4.2 Synchronization to SYSCLKOUT Only
      3. 8.4.3 Qualification Using a Sampling Window
    5. 8.5  USB Signals
    6. 8.6  SPI Signals
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Software
      1. 8.9.1 GPIO Examples
        1. 8.9.1.1 Device GPIO Setup
        2. 8.9.1.2 Device GPIO Toggle
        3. 8.9.1.3 Device GPIO Interrupt
      2. 8.9.2 LED Examples
    10. 8.10 GPIO Registers
      1. 8.10.1 GPIO Base Addresses
      2. 8.10.2 GPIO_CTRL_REGS Registers
      3. 8.10.3 GPIO_DATA_REGS Registers
      4. 8.10.4 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 ePWM, CLB, and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 CLB X-BAR
        1. 9.2.2.1 CLB X-BAR Architecture
      3. 9.2.3 GPIO Output X-BAR
        1. 9.2.3.1 GPIO Output X-BAR Architecture
      4. 9.2.4 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Addresses
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 CLB_XBAR_REGS Registers
      6. 9.3.6 OUTPUT_XBAR_REGS Registers
      7. 9.3.7 Register to Driverlib Function Mapping
        1. 9.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.7.2 XBAR Registers to Driverlib Functions
        3. 9.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 9.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  12. 10Analog Subsystem
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Optimizing Power-Up Time
    3. 10.3 Analog Subsystem Registers
      1. 10.3.1 Analog Subsystem Base Addresses
      2. 10.3.2 ANALOG_SUBSYS_REGS Registers
  13. 11Analog-to-Digital Converter (ADC)
    1. 11.1  Introduction
      1. 11.1.1 ADC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2  ADC Configurability
      1. 11.2.1 Clock Configuration
      2. 11.2.2 Resolution
      3. 11.2.3 Voltage Reference
        1. 11.2.3.1 External Reference Mode
      4. 11.2.4 Signal Mode
      5. 11.2.5 Expected Conversion Results
      6. 11.2.6 Interpreting Conversion Results
    3. 11.3  SOC Principle of Operation
      1. 11.3.1 SOC Configuration
      2. 11.3.2 Trigger Operation
      3. 11.3.3 ADC Acquisition (Sample and Hold) Window
      4. 11.3.4 ADC Input Models
      5. 11.3.5 Channel Selection
    4. 11.4  SOC Configuration Examples
      1. 11.4.1 Single Conversion from ePWM Trigger
      2. 11.4.2 Oversampled Conversion from ePWM Trigger
      3. 11.4.3 Multiple Conversions from CPU Timer Trigger
      4. 11.4.4 Software Triggering of SOCs
    5. 11.5  ADC Conversion Priority
    6. 11.6  Burst Mode
      1. 11.6.1 Burst Mode Example
      2. 11.6.2 Burst Mode Priority Example
    7. 11.7  EOC and Interrupt Operation
      1. 11.7.1 Interrupt Overflow
      2. 11.7.2 Continue to Interrupt Mode
      3. 11.7.3 Early Interrupt Configuration Mode
    8. 11.8  Post-Processing Blocks
      1. 11.8.1 PPB Offset Correction
      2. 11.8.2 PPB Error Calculation
      3. 11.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 11.8.4 PPB Sample Delay Capture
    9. 11.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 11.9.1 Implementation
      2. 11.9.2 Detecting an Open Input Pin
      3. 11.9.3 Detecting a Shorted Input Pin
    10. 11.10 Power-Up Sequence
    11. 11.11 ADC Calibration
      1. 11.11.1 ADC Zero Offset Calibration
      2. 11.11.2 ADC Calibration Routines in OTP Memory
    12. 11.12 ADC Timings
      1. 11.12.1 ADC Timing Diagrams
    13. 11.13 Additional Information
      1. 11.13.1 Ensuring Synchronous Operation
        1. 11.13.1.1 Basic Synchronous Operation
        2. 11.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 11.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 11.13.1.4 Synchronous Operation with Different Resolutions
        5. 11.13.1.5 Non-overlapping Conversions
      2. 11.13.2 Choosing an Acquisition Window Duration
      3. 11.13.3 Achieving Simultaneous Sampling
      4. 11.13.4 Result Register Mapping
      5. 11.13.5 Internal Temperature Sensor
      6. 11.13.6 Designing an External Reference Circuit
    14. 11.14 Software
      1. 11.14.1 ADC Examples
        1. 11.14.1.1  ADC Software Triggering
        2. 11.14.1.2  ADC ePWM Triggering
        3. 11.14.1.3  ADC Temperature Sensor Conversion
        4. 11.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 11.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 11.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 11.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 11.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 11.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 11.14.1.10 ADC Burst Mode
        11. 11.14.1.11 ADC Burst Mode Oversampling
        12. 11.14.1.12 ADC SOC Oversampling
        13. 11.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
    15. 11.15 ADC Registers
      1. 11.15.1 ADC Base Addresses
      2. 11.15.2 ADC_RESULT_REGS Registers
      3. 11.15.3 ADC_REGS Registers
      4. 11.15.4 ADC Registers to Driverlib Functions
  14. 12Buffered Digital-to-Analog Converter (DAC)
    1. 12.1 Introduction
      1. 12.1.1 DAC Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Block Diagram
    2. 12.2 Using the DAC
      1. 12.2.1 Initialization Sequence
      2. 12.2.2 DAC Offset Adjustment
      3. 12.2.3 EPWMSYNCPER Signal
    3. 12.3 Lock Registers
    4. 12.4 Software
      1. 12.4.1 DAC Examples
        1. 12.4.1.1 Buffered DAC Enable
        2. 12.4.1.2 Buffered DAC Random
        3. 12.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 12.5 DAC Registers
      1. 12.5.1 DAC Base Addresses
      2. 12.5.2 DAC_REGS Registers
      3. 12.5.3 DAC Registers to Driverlib Functions
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 CMPSS Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Ramp Generator
      1. 13.4.1 Ramp Generator Overview
      2. 13.4.2 Ramp Generator Behavior
      3. 13.4.3 Ramp Generator Behavior at Corner Cases
    5. 13.5 Digital Filter
      1. 13.5.1 Filter Initialization Sequence
    6. 13.6 Using the CMPSS
      1. 13.6.1 LATCHCLR and EPWMSYNCPER Signals
      2. 13.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.6.3 Calibrating the CMPSS
      4. 13.6.4 Enabling and Disabling the CMPSS Clock
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
        1. 13.7.1.1 CMPSS Asynchronous Trip
        2. 13.7.1.2 CMPSS Digital Filter Configuration
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Addresses
      2. 13.8.2 CMPSS_REGS Registers
      3. 13.8.3 CMPSS Registers to Driverlib Functions
  16. 14Sigma Delta Filter Module (SDFM)
    1. 14.1  Introduction
      1. 14.1.1 SDFM Related Collateral
      2. 14.1.2 Features
      3. 14.1.3 Block Diagram
    2. 14.2  Configuring Device Pins
    3. 14.3  Input Control Unit
    4. 14.4  Sinc Filter
      1. 14.4.1 Data Rate and Latency of the Sinc Filter
    5. 14.5  Data (Primary) Filter Unit
      1. 14.5.1 32-bit or 16-bit Data Filter Output Representation
      2. 14.5.2 SDSYNC Event
    6. 14.6  Comparator (Secondary) Filter Unit
      1. 14.6.1 Higher Threshold (HLT) Comparator
      2. 14.6.2 Lower Threshold (LLT) Comparator
    7. 14.7  Theoretical SDFM Filter Output
    8. 14.8  Interrupt Unit
      1. 14.8.1 SDFM (SDINT) Interrupt Sources
    9. 14.9  Register Descriptions
    10. 14.10 Software
      1. 14.10.1 SDFM Examples
    11. 14.11 SDFM Registers
      1. 14.11.1 SDFM Base Addresses
      2. 14.11.2 SDFM_REGS Registers
      3. 14.11.3 SDFM Registers to Driverlib Functions
  17. 15Enhanced Pulse Width Modulator (ePWM)
    1. 15.1  Introduction
      1. 15.1.1 EPWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  ePWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 15.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 15.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 15.4.7 Global Load
        1. 15.4.7.1 Global Load Pulse Pre-Scalar
        2. 15.4.7.2 One-Shot Load Mode
        3. 15.4.7.3 One-Shot Sync Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  PWM Chopper (PC) Submodule
      1. 15.8.1 Purpose of the PWM Chopper Submodule
      2. 15.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 15.8.3 Waveforms
        1. 15.8.3.1 One-Shot Pulse
        2. 15.8.3.2 Duty Cycle Control
    9. 15.9  Trip-Zone (TZ) Submodule
      1. 15.9.1 Purpose of the Trip-Zone Submodule
      2. 15.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.9.2.1 Trip-Zone Configurations
      3. 15.9.3 Generating Trip Event Interrupts
    10. 15.10 Event-Trigger (ET) Submodule
      1. 15.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 15.11 Digital Compare (DC) Submodule
      1. 15.11.1 Purpose of the Digital Compare Submodule
      2. 15.11.2 Enhanced Trip Action Using CMPSS
      3. 15.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 15.11.4 Operation Highlights of the Digital Compare Submodule
        1. 15.11.4.1 Digital Compare Events
        2. 15.11.4.2 Event Filtering
        3. 15.11.4.3 Valley Switching
    12. 15.12 ePWM Crossbar (X-BAR)
    13. 15.13 Applications to Power Topologies
      1. 15.13.1  Overview of Multiple Modules
      2. 15.13.2  Key Configuration Capabilities
      3. 15.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 15.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 15.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 15.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 15.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 15.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 15.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 15.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 15.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 15.14 High-Resolution Pulse Width Modulator (HRPWM)
      1. 15.14.1 Operational Description of HRPWM
        1. 15.14.1.1 Controlling the HRPWM Capabilities
        2. 15.14.1.2 HRPWM Source Clock
        3. 15.14.1.3 Configuring the HRPWM
        4. 15.14.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 15.14.1.5 Principle of Operation
          1. 15.14.1.5.1 Edge Positioning
          2. 15.14.1.5.2 Scaling Considerations
          3. 15.14.1.5.3 Duty Cycle Range Limitation
          4. 15.14.1.5.4 High-Resolution Period
            1. 15.14.1.5.4.1 High-Resolution Period Configuration
        6. 15.14.1.6 Deadband High-Resolution Operation
        7. 15.14.1.7 Scale Factor Optimizing Software (SFO)
        8. 15.14.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 15.14.1.8.1 #Defines for HRPWM Header Files
          2. 15.14.1.8.2 Implementing a Simple Buck Converter
            1. 15.14.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 15.14.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 15.14.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 15.14.1.8.3.1 PWM DAC Function Initialization Code
            2. 15.14.1.8.3.2 PWM DAC Function Run-Time Code
      2. 15.14.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 15.14.2.1 Scale Factor Optimizer Function - int SFO()
        2. 15.14.2.2 Software Usage
          1. 15.14.2.2.1 A Sample of How to Add "Include" Files
          2.        762
          3. 15.14.2.2.2 Declaring an Element
          4.        764
          5. 15.14.2.2.3 Initializing With a Scale Factor Value
          6.        766
          7. 15.14.2.2.4 SFO Function Calls
    15. 15.15 ePWM Registers
      1. 15.15.1 ePWM Base Addresses
      2. 15.15.2 EPWM_REGS Registers
      3. 15.15.3 Register to Driverlib Function Mapping
        1. 15.15.3.1 EPWM Registers to Driverlib Functions
        2. 15.15.3.2 HRPWM Registers to Driverlib Functions
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1  Event Prescaler
      2. 16.5.2  Edge Polarity Select and Qualifier
      3. 16.5.3  Continuous/One-Shot Control
      4. 16.5.4  32-Bit Counter and Phase Control
      5. 16.5.5  CAP1-CAP4 Registers
      6. 16.5.6  eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7  Interrupt Control
      8. 16.5.8  DMA Interrupt
      9. 16.5.9  Shadow Load and Lockout Control
      10. 16.5.10 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
        3. 16.8.1.3 eCAP APWM Phase-shift Example
        4. 16.8.1.4 eCAP Software Sync Example
    9. 16.9 eCAP Registers
      1. 16.9.1 eCAP Base Addresses
      2. 16.9.2 ECAP_REGS Registers
      3. 16.9.3 ECAP Registers to Driverlib Functions
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  eQEP Interrupt Structure
    10. 17.10 eQEP Registers
      1. 17.10.1 eQEP Base Addresses
      2. 17.10.2 EQEP_REGS Registers
      3. 17.10.3 EQEP Registers to Driverlib Functions
  20. 18Serial Peripheral Interface (SPI)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 SPI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2 System-Level Integration
      1. 18.2.1 SPI Module Signals
      2. 18.2.2 Configuring Device Pins
        1. 18.2.2.1 GPIOs Required for High-Speed Mode
      3. 18.2.3 SPI Interrupts
      4. 18.2.4 DMA Support
    3. 18.3 SPI Operation
      1. 18.3.1  Introduction to Operation
      2. 18.3.2  Master Mode
      3. 18.3.3  Slave Mode
      4. 18.3.4  Data Format
        1. 18.3.4.1 Transmission of Bit from SPIRXBUF
      5. 18.3.5  Baud Rate Selection
        1. 18.3.5.1 Baud Rate Determination
        2. 18.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 18.3.6  SPI Clocking Schemes
      7. 18.3.7  SPI FIFO Description
      8. 18.3.8  SPI DMA Transfers
        1. 18.3.8.1 Transmitting Data Using SPI with DMA
        2. 18.3.8.2 Receiving Data Using SPI with DMA
      9. 18.3.9  SPI High-Speed Mode
      10. 18.3.10 SPI 3-Wire Mode Description
    4. 18.4 Programming Procedure
      1. 18.4.1 Initialization Upon Reset
      2. 18.4.2 Configuring the SPI
      3. 18.4.3 Configuring the SPI for High-Speed Mode
      4. 18.4.4 Data Transfer Example
      5. 18.4.5 SPI 3-Wire Mode Code Examples
        1. 18.4.5.1 3-Wire Master Mode Transmit
        2.       879
          1. 18.4.5.2.1 3-Wire Master Mode Receive
        3.       881
          1. 18.4.5.2.1 3-Wire Slave Mode Transmit
        4.       883
          1. 18.4.5.2.1 3-Wire Slave Mode Receive
      6. 18.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 18.5 Software
      1. 18.5.1 SPI Examples
        1. 18.5.1.1 SPI Digital Loopback
        2. 18.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 18.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 18.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 18.5.1.5 SPI Digital Loopback with DMA
        6. 18.5.1.6 SPI EEPROM
        7. 18.5.1.7 SPI DMA EEPROM
    6. 18.6 SPI Registers
      1. 18.6.1 SPI Base Addresses
      2. 18.6.2 SPI_REGS Registers
      3. 18.6.3 SPI Registers to Driverlib Functions
  21. 19Serial Communications Interface (SCI)
    1. 19.1  Introduction
      1. 19.1.1 Features
      2. 19.1.2 SCI Related Collateral
      3. 19.1.3 Block Diagram
    2. 19.2  Architecture
    3. 19.3  SCI Module Signal Summary
    4. 19.4  Configuring Device Pins
    5. 19.5  Multiprocessor and Asynchronous Communication Modes
    6. 19.6  SCI Programmable Data Format
    7. 19.7  SCI Multiprocessor Communication
      1. 19.7.1 Recognizing the Address Byte
      2. 19.7.2 Controlling the SCI TX and RX Features
      3. 19.7.3 Receipt Sequence
    8. 19.8  Idle-Line Multiprocessor Mode
      1. 19.8.1 Idle-Line Mode Steps
      2. 19.8.2 Block Start Signal
      3. 19.8.3 Wake-Up Temporary (WUT) Flag
        1. 19.8.3.1 Sending a Block Start Signal
      4. 19.8.4 Receiver Operation
    9. 19.9  Address-Bit Multiprocessor Mode
      1. 19.9.1 Sending an Address
    10. 19.10 SCI Communication Format
      1. 19.10.1 Receiver Signals in Communication Modes
      2. 19.10.2 Transmitter Signals in Communication Modes
    11. 19.11 SCI Port Interrupts
      1. 19.11.1 Break Detect
    12. 19.12 SCI Baud Rate Calculations
    13. 19.13 SCI Enhanced Features
      1. 19.13.1 SCI FIFO Description
      2. 19.13.2 SCI Auto-Baud
      3. 19.13.3 Autobaud-Detect Sequence
    14. 19.14 Software
      1. 19.14.1 SCI Examples
    15. 19.15 SCI Registers
      1. 19.15.1 SCI Base Addresses
      2. 19.15.2 SCI_REGS Registers
      3. 19.15.3 SCI Registers to Driverlib Functions
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Master Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Arbitration
      10. 20.3.10 Digital Loopback Mode
      11. 20.3.11 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Examples
        1. 20.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 20.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 20.6.1.5 I2C EEPROM
        6. 20.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 20.6.1.7 I2C EEPROM
        8. 20.6.1.8 I2C controller target communication using FIFO interrupts
        9. 20.6.1.9 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Addresses
      2. 20.7.2 I2C_REGS Registers
      3. 20.7.3 I2C Registers to Driverlib Functions
  23. 21Multichannel Buffered Serial Port (McBSP)
    1. 21.1  Introduction
      1. 21.1.1 MCBSP Related Collateral
      2. 21.1.2 Features of the McBSPs
      3. 21.1.3 McBSP Pins/Signals
        1. 21.1.3.1 McBSP Generic Block Diagram
    2. 21.2  Configuring Device Pins
    3. 21.3  McBSP Operation
      1. 21.3.1 Data Transfer Process of McBSPs
        1. 21.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 21.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 21.3.2 Companding (Compressing and Expanding) Data
        1. 21.3.2.1 Companding Formats
        2. 21.3.2.2 Capability to Compand Internal Data
        3. 21.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 21.3.3 Clocking and Framing Data
        1. 21.3.3.1 Clocking
        2. 21.3.3.2 Serial Words
        3. 21.3.3.3 Frames and Frame Synchronization
        4. 21.3.3.4 Generating Transmit and Receive Interrupts
          1. 21.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 21.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 21.3.3.6 Frame Frequency
        7. 21.3.3.7 Maximum Frame Frequency
      4. 21.3.4 Frame Phases
        1. 21.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 21.3.4.2 Single-Phase Frame Example
        3. 21.3.4.3 Dual-Phase Frame Example
        4. 21.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 21.3.5 McBSP Reception
      6. 21.3.6 McBSP Transmission
      7. 21.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 21.4  McBSP Sample Rate Generator
      1. 21.4.1 Block Diagram
        1. 21.4.1.1 Clock Generation in the Sample Rate Generator
        2. 21.4.1.2 Choosing an Input Clock
        3. 21.4.1.3 Choosing a Polarity for the Input Clock
        4. 21.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 21.4.1.4.1 CLKG Frequency
        5. 21.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 21.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 21.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 21.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 21.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 21.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 21.4.3.2 Synchronization Examples
      4. 21.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 21.5  McBSP Exception/Error Conditions
      1. 21.5.1 Types of Errors
      2. 21.5.2 Overrun in the Receiver
        1. 21.5.2.1 Example of Overrun Condition
        2. 21.5.2.2 Example of Preventing Overrun Condition
      3. 21.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 21.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 21.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 21.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 21.5.4 Overwrite in the Transmitter
        1. 21.5.4.1 Example of Overwrite Condition
        2. 21.5.4.2 Preventing Overwrites
      5. 21.5.5 Underflow in the Transmitter
        1. 21.5.5.1 Example of the Underflow Condition
        2. 21.5.5.2 Example of Preventing Underflow Condition
      6. 21.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 21.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 21.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 21.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 21.6  Multichannel Selection Modes
      1. 21.6.1 Channels, Blocks, and Partitions
      2. 21.6.2 Multichannel Selection
      3. 21.6.3 Configuring a Frame for Multichannel Selection
      4. 21.6.4 Using Two Partitions
        1. 21.6.4.1 Assigning Blocks to Partitions A and B
        2. 21.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 21.6.5 Using Eight Partitions
      6. 21.6.6 Receive Multichannel Selection Mode
      7. 21.6.7 Transmit Multichannel Selection Modes
        1. 21.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 21.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 21.6.8 Using Interrupts Between Block Transfers
    7. 21.7  SPI Operation Using the Clock Stop Mode
      1. 21.7.1 SPI Protocol
      2. 21.7.2 Clock Stop Mode
      3. 21.7.3 Enable and Configure the Clock Stop Mode
      4. 21.7.4 Clock Stop Mode Timing Diagrams
      5. 21.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 21.7.6 McBSP as the SPI Master
      7. 21.7.7 McBSP as an SPI Slave
    8. 21.8  Receiver Configuration
      1. 21.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 21.8.2  Resetting and Enabling the Receiver
        1. 21.8.2.1 Reset Considerations
      3. 21.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 21.8.4  Digital Loopback Mode
      5. 21.8.5  Clock Stop Mode
      6. 21.8.6  Receive Multichannel Selection Mode
      7. 21.8.7  Receive Frame Phases
      8. 21.8.8  Receive Word Lengths
        1. 21.8.8.1 Word Length Bits
      9. 21.8.9  Receive Frame Length
        1. 21.8.9.1 Selected Frame Length
      10. 21.8.10 Receive Frame-Synchronization Ignore Function
        1. 21.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 21.8.10.2 Examples of Effects of RFIG
      11. 21.8.11 Receive Companding Mode
        1. 21.8.11.1 Companding
        2. 21.8.11.2 Format of Expanded Data
        3. 21.8.11.3 Companding Internal Data
        4. 21.8.11.4 Option to Receive LSB First
      12. 21.8.12 Receive Data Delay
        1. 21.8.12.1 Data Delay
        2. 21.8.12.2 0-Bit Data Delay
        3. 21.8.12.3 2-Bit Data Delay
      13. 21.8.13 Receive Sign-Extension and Justification Mode
        1. 21.8.13.1 Sign-Extension and the Justification
      14. 21.8.14 Receive Interrupt Mode
      15. 21.8.15 Receive Frame-Synchronization Mode
        1. 21.8.15.1 Receive Frame-Synchronization Modes
      16. 21.8.16 Receive Frame-Synchronization Polarity
        1. 21.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 21.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 21.8.17 Receive Clock Mode
        1. 21.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 21.8.18 Receive Clock Polarity
        1. 21.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 21.8.19 SRG Clock Divide-Down Value
        1. 21.8.19.1 Sample Rate Generator Clock Divider
      20. 21.8.20 SRG Clock Synchronization Mode
      21. 21.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 21.8.22 SRG Input Clock Polarity
        1. 21.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 21.9  Transmitter Configuration
      1. 21.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 21.9.2  Resetting and Enabling the Transmitter
        1. 21.9.2.1 Reset Considerations
      3. 21.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 21.9.4  Digital Loopback Mode
      5. 21.9.5  Clock Stop Mode
      6. 21.9.6  Transmit Multichannel Selection Mode
      7. 21.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 21.9.8  Transmit Frame Phases
      9. 21.9.9  Transmit Word Lengths
        1. 21.9.9.1 Word Length Bits
      10. 21.9.10 Transmit Frame Length
        1. 21.9.10.1 Selected Frame Length
      11. 21.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 21.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 21.9.11.2 Examples Showing the Effects of XFIG
      12. 21.9.12 Transmit Companding Mode
        1. 21.9.12.1 Companding
        2. 21.9.12.2 Format for Data To Be Compressed
        3. 21.9.12.3 Capability to Compand Internal Data
        4. 21.9.12.4 Option to Transmit LSB First
      13. 21.9.13 Transmit Data Delay
        1. 21.9.13.1 Data Delay
        2. 21.9.13.2 0-Bit Data Delay
        3. 21.9.13.3 2-Bit Data Delay
      14. 21.9.14 Transmit DXENA Mode
      15. 21.9.15 Transmit Interrupt Mode
      16. 21.9.16 Transmit Frame-Synchronization Mode
        1. 21.9.16.1 Other Considerations
      17. 21.9.17 Transmit Frame-Synchronization Polarity
        1. 21.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 21.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 21.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 21.9.19 Transmit Clock Mode
        1. 21.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 21.9.19.2 Other Considerations
      20. 21.9.20 Transmit Clock Polarity
        1. 21.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 21.10 Emulation and Reset Considerations
      1. 21.10.1 McBSP Emulation Mode
      2. 21.10.2 Resetting and Initializing McBSPs
        1. 21.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 21.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 21.10.2.3 McBSP Initialization Procedure
        4. 21.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 21.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 21.11 Data Packing Examples
      1. 21.11.1 Data Packing Using Frame Length and Word Length
      2. 21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 21.12 Interrupt Generation
      1. 21.12.1 McBSP Receive Interrupt Generation
      2. 21.12.2 McBSP Transmit Interrupt Generation
      3. 21.12.3 Error Flags
    13. 21.13 McBSP Modes
    14. 21.14 Special Case: External Device is the Transmit Frame Master
    15. 21.15 Software
      1. 21.15.1 MCBSP Examples
    16. 21.16 McBSP Registers
      1. 21.16.1 McBSP Base Addresses
      2. 21.16.2 McBSP_REGS Registers
      3. 21.16.3 MCBSP Registers to Driverlib Functions
  24. 22Controller Area Network (CAN)
    1. 22.1  Introduction
      1. 22.1.1 DCAN Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Block Diagram
        1. 22.1.3.1 CAN Core
        2. 22.1.3.2 Message Handler
        3. 22.1.3.3 Message RAM
        4. 22.1.3.4 Registers and Message Object Access (IFx)
    2. 22.2  Functional Description
      1. 22.2.1 Configuring Device Pins
      2. 22.2.2 Address/Data Bus Bridge
    3. 22.3  Operating Modes
      1. 22.3.1 Initialization
      2. 22.3.2 CAN Message Transfer (Normal Operation)
        1. 22.3.2.1 Disabled Automatic Retransmission
        2. 22.3.2.2 Auto-Bus-On
      3. 22.3.3 Test Modes
        1. 22.3.3.1 Silent Mode
        2. 22.3.3.2 Loopback Mode
        3. 22.3.3.3 External Loopback Mode
        4. 22.3.3.4 Loopback Combined with Silent Mode
    4. 22.4  Multiple Clock Source
    5. 22.5  Interrupt Functionality
      1. 22.5.1 Message Object Interrupts
      2. 22.5.2 Status Change Interrupts
      3. 22.5.3 Error Interrupts
      4. 22.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 22.5.5 Interrupt Topologies
    6. 22.6  Parity Check Mechanism
      1. 22.6.1 Behavior on Parity Error
    7. 22.7  Debug Mode
    8. 22.8  Module Initialization
    9. 22.9  Configuration of Message Objects
      1. 22.9.1 Configuration of a Transmit Object for Data Frames
      2. 22.9.2 Configuration of a Transmit Object for Remote Frames
      3. 22.9.3 Configuration of a Single Receive Object for Data Frames
      4. 22.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 22.9.5 Configuration of a FIFO Buffer
    10. 22.10 Message Handling
      1. 22.10.1  Message Handler Overview
      2. 22.10.2  Receive/Transmit Priority
      3. 22.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 22.10.4  Updating a Transmit Object
      5. 22.10.5  Changing a Transmit Object
      6. 22.10.6  Acceptance Filtering of Received Messages
      7. 22.10.7  Reception of Data Frames
      8. 22.10.8  Reception of Remote Frames
      9. 22.10.9  Reading Received Messages
      10. 22.10.10 Requesting New Data for a Receive Object
      11. 22.10.11 Storing Received Messages in FIFO Buffers
      12. 22.10.12 Reading from a FIFO Buffer
    11. 22.11 CAN Bit Timing
      1. 22.11.1 Bit Time and Bit Rate
        1. 22.11.1.1 Synchronization Segment
        2. 22.11.1.2 Propagation Time Segment
        3. 22.11.1.3 Phase Buffer Segments and Synchronization
        4. 22.11.1.4 Oscillator Tolerance Range
      2. 22.11.2 Configuration of the CAN Bit Timing
        1. 22.11.2.1 Calculation of the Bit Timing Parameters
        2. 22.11.2.2 Example for Bit Timing at High Baudrate
        3. 22.11.2.3 Example for Bit Timing at Low Baudrate
    12. 22.12 Message Interface Register Sets
      1. 22.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 22.12.2 Message Interface Register Set 3 (IF3)
    13. 22.13 Message RAM
      1. 22.13.1 Structure of Message Objects
      2. 22.13.2 Addressing Message Objects in RAM
      3. 22.13.3 Message RAM Representation in Debug Mode
    14. 22.14 Software
      1. 22.14.1 CAN Examples
    15. 22.15 CAN Registers
      1. 22.15.1 CAN Base Addresses
      2. 22.15.2 CAN_REGS Registers
      3. 22.15.3 CAN Registers to Driverlib Functions
  25. 23Universal Serial Bus (USB) Controller
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 USB Related Collateral
      3. 23.1.3 Block Diagram
        1. 23.1.3.1 Signal Description
        2. 23.1.3.2 VBus Recommendations
    2. 23.2 Functional Description
      1. 23.2.1 Operation as a Device
        1. 23.2.1.1 Control and Configurable Endpoints
          1. 23.2.1.1.1 IN Transactions as a Device
          2. 23.2.1.1.2 Out Transactions as a Device
          3. 23.2.1.1.3 Scheduling
          4. 23.2.1.1.4 Additional Actions
          5. 23.2.1.1.5 Device Mode Suspend
          6. 23.2.1.1.6 Start of Frame
          7. 23.2.1.1.7 USB Reset
          8. 23.2.1.1.8 Connect/Disconnect
      2. 23.2.2 Operation as a Host
        1. 23.2.2.1 Endpoint Registers
        2. 23.2.2.2 IN Transactions as a Host
        3. 23.2.2.3 OUT Transactions as a Host
        4. 23.2.2.4 Transaction Scheduling
        5. 23.2.2.5 USB Hubs
        6. 23.2.2.6 Babble
        7. 23.2.2.7 Host SUSPEND
        8. 23.2.2.8 USB RESET
        9. 23.2.2.9 Connect/Disconnect
      3. 23.2.3 DMA Operation
      4. 23.2.4 Address/Data Bus Bridge
    3. 23.3 Initialization and Configuration
      1. 23.3.1 Pin Configuration
      2. 23.3.2 Endpoint Configuration
    4. 23.4 USB Global Interrupts
    5. 23.5 Software
      1. 23.5.1 USB Examples
    6. 23.6 USB Registers
      1. 23.6.1 USB Base Address
      2. 23.6.2 USB Register Map
      3. 23.6.3 Register Descriptions
        1. 23.6.3.1  USB Device Functional Address Register (USBFADDR), offset 0x000
        2. 23.6.3.2  USB Power Management Register (USBPOWER), offset 0x001
        3. 23.6.3.3  USB Transmit Interrupt Status Register
        4. 23.6.3.4  USB Receive Interrupt Status Register
        5. 23.6.3.5  USB Transmit Interrupt Enable Register
        6. 23.6.3.6  USB Receive Interrupt Enable Register
        7. 23.6.3.7  USB General Interrupt Status Register (USBIS), offset 0x00A
        8. 23.6.3.8  USB Interrupt Enable Register (USBIE), offset 0x00B
        9. 23.6.3.9  USB Frame Value Register (USBFRAME), offset 0x00C
        10. 23.6.3.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
        11. 23.6.3.11 USB Test Mode Register (USBTEST), offset 0x00F
        12. 23.6.3.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
        13. 23.6.3.13 USB Device Control Register (USBDEVCTL), offset 0x060
        14. 23.6.3.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
        15. 23.6.3.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
        16. 23.6.3.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
        17. 23.6.3.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
        18. 23.6.3.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
        19. 23.6.3.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
        20. 23.6.3.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
        21. 23.6.3.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[n])
        22. 23.6.3.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[n])
        23. 23.6.3.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[n])
        24. 23.6.3.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[n)
        25. 23.6.3.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[n])
        26. 23.6.3.26 USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[1]-USBRXHUBPORT[n])
        27. 23.6.3.27 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
        28. 23.6.3.28 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
        29. 23.6.3.29 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
        30. 23.6.3.30 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
        31. 23.6.3.31 USB NAK Limit Register (USBNAKLMT), offset 0x10B
        32. 23.6.3.32 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[n])
        33. 23.6.3.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[n])
        34. 23.6.3.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[n])
        35. 23.6.3.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[n])
        36. 23.6.3.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[n])
        37. 23.6.3.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[n])
        38. 23.6.3.38 USB Receive Byte Count Endpoint n Register (USBRXCOUNT[1]-USBRXCOUNT[n])
        39. 23.6.3.39 USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[1]-USBTXTYPE[n])
        40. 23.6.3.40 USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[1]-USBTXINTERVAL[n])
        41. 23.6.3.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[n])
        42. 23.6.3.42 USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[1]-USBRXINTERVAL[n])
        43. 23.6.3.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[n])
        44. 23.6.3.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
        45. 23.6.3.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
        46. 23.6.3.46 USB External Power Control Register (USBEPC), offset 0x400
        47. 23.6.3.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
        48. 23.6.3.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
        49. 23.6.3.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
        50. 23.6.3.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
        51. 23.6.3.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
        52. 23.6.3.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
        53. 23.6.3.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
        54. 23.6.3.54 USB DMA Select Register (USBDMASEL), offset 0x450
      4. 23.6.4 USB Registers to Driverlib Functions
  26. 24Universal Parallel Port (uPP)
    1. 24.1 Introduction
      1. 24.1.1 Features Supported
    2. 24.2 Configuring Device Pins
    3. 24.3 Functional Description
      1. 24.3.1 Functional Block Diagram
      2. 24.3.2 Data Flow
      3. 24.3.3 Clock Generation and Control
    4. 24.4 IO Interface and System Requirements
      1. 24.4.1  Pin Multiplexing
      2. 24.4.2  Internal DMA Controller Description
        1. 24.4.2.1 DMA Programming Concepts
        2. 24.4.2.2 Data Interleave Mode
      3. 24.4.3  Protocol Description
        1. 24.4.3.1 DATA[7:0] Signals
        2. 24.4.3.2 START Signal
        3. 24.4.3.3 ENABLE
        4. 24.4.3.4 WAIT Signal
        5. 24.4.3.5 CLOCK Signal
        6. 24.4.3.6 Signal Timing Diagrams
      4. 24.4.4  Data Format
      5. 24.4.5  Reset Considerations
        1. 24.4.5.1 Software Reset
        2. 24.4.5.2 Hardware Reset
      6. 24.4.6  Interrupt Support
        1. 24.4.6.1 End of Line (EOL) Event
        2. 24.4.6.2 End of Window (EOW) Event
        3. 24.4.6.3 Underrun or Overflow (UOR) Event
        4. 24.4.6.4 DMA Programming Error (DPE) Event
      7. 24.4.7  Emulation Considerations
      8. 24.4.8  Transmit and Receive FIFOs
      9. 24.4.9  Transmit and Receive Data (MSG) RAM
      10. 24.4.10 Initialization and Operation
        1. 24.4.10.1 System Tuning Tips
    5. 24.5 UPP Registers
      1. 24.5.1 UPP Base Addresses
      2. 24.5.2 UPP_REGS Registers
      3. 24.5.3 UPP Registers to Driverlib Functions
  27. 25External Memory Interface (EMIF)
    1. 25.1 Introduction
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 EMIF Related Collateral
      3. 25.1.3 Features
        1. 25.1.3.1 Asynchronous Memory Support
        2. 25.1.3.2 Synchronous DRAM Memory Support
      4. 25.1.4 Functional Block Diagram
      5. 25.1.5 Configuring Device Pins
    2. 25.2 EMIF Module Architecture
      1. 25.2.1  EMIF Clock Control
      2. 25.2.2  EMIF Requests
      3. 25.2.3  EMIF Signal Descriptions
      4. 25.2.4  EMIF Signal Multiplexing Control
      5. 25.2.5  SDRAM Controller and Interface
        1. 25.2.5.1  SDRAM Commands
        2. 25.2.5.2  Interfacing to SDRAM
        3. 25.2.5.3  SDRAM Configuration Registers
        4. 25.2.5.4  SDRAM Auto-Initialization Sequence
        5. 25.2.5.5  SDRAM Configuration Procedure
        6. 25.2.5.6  EMIF Refresh Controller
          1. 25.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 25.2.5.7  Self-Refresh Mode
        8. 25.2.5.8  Power-Down Mode
        9. 25.2.5.9  SDRAM Read Operation
        10. 25.2.5.10 SDRAM Write Operations
        11. 25.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 25.2.6  Asynchronous Controller and Interface
        1. 25.2.6.1 Interfacing to Asynchronous Memory
        2. 25.2.6.2 Accessing Larger Asynchronous Memories
        3. 25.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 25.2.6.4 Read and Write Operations in Normal Mode
          1. 25.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 25.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 25.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 25.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 25.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 25.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 25.2.7  Data Bus Parking
      8. 25.2.8  Reset and Initialization Considerations
      9. 25.2.9  Interrupt Support
        1. 25.2.9.1 Interrupt Events
      10. 25.2.10 DMA Event Support
      11. 25.2.11 EMIF Signal Multiplexing
      12. 25.2.12 Memory Map
      13. 25.2.13 Priority and Arbitration
      14. 25.2.14 System Considerations
        1. 25.2.14.1 Asynchronous Request Times
      15. 25.2.15 Power Management
        1. 25.2.15.1 Power Management Using Self-Refresh Mode
        2. 25.2.15.2 Power Management Using Power Down Mode
      16. 25.2.16 Emulation Considerations
    3. 25.3 Example Configuration
      1. 25.3.1 Hardware Interface
      2. 25.3.2 Software Configuration
        1. 25.3.2.1 Configuring the SDRAM Interface
          1. 25.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 25.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 25.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 25.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 25.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 25.3.2.2 Configuring the Flash Interface
          1. 25.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 25.4 EMIF Registers
      1. 25.4.1 EMIF Base Addresses
      2. 25.4.2 EMIF_REGS Registers
      3. 25.4.3 EMIF1_CONFIG_REGS Registers
      4. 25.4.4 EMIF2_CONFIG_REGS Registers
      5. 25.4.5 EMIF Registers to Driverlib Functions
  28. 26Configurable Logic Block (CLB)
    1. 26.1 Introduction
      1. 26.1.1 CLB Related Collateral
    2. 26.2 Description
      1. 26.2.1 CLB Clock
    3. 26.3 CLB Input/Output Connection
      1. 26.3.1 Overview
      2. 26.3.2 CLB Input Selection
      3. 26.3.3 CLB Output Selection
      4. 26.3.4 CLB Output Signal Multiplexer
    4. 26.4 CLB Tile
      1. 26.4.1 Static Switch Block
      2. 26.4.2 Counter Block
        1. 26.4.2.1 Counter Description
        2. 26.4.2.2 Counter Operation
      3. 26.4.3 FSM Block
      4. 26.4.4 LUT4 Block
      5. 26.4.5 Output LUT Block
      6. 26.4.6 High Level Controller (HLC)
        1. 26.4.6.1 High Level Controller Events
        2. 26.4.6.2 High Level Controller Instructions
        3. 26.4.6.3 <Src> and <Dest>
        4. 26.4.6.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 26.5 CPU Interface
      1. 26.5.1 Register Description
      2. 26.5.2 Non-Memory Mapped Registers
    6. 26.6 DMA Access
    7. 26.7 Software
      1. 26.7.1 CLB Examples
        1. 26.7.1.1  CLB Empty Project
        2. 26.7.1.2  CLB Combinational Logic
        3. 26.7.1.3  CLB GPIO Input Filter
        4. 26.7.1.4  CLB Auxilary PWM
        5. 26.7.1.5  CLB PWM Protection
        6. 26.7.1.6  CLB Event Window
        7. 26.7.1.7  CLB Signal Generator
        8. 26.7.1.8  CLB State Machine
        9. 26.7.1.9  CLB External Signal AND Gate
        10. 26.7.1.10 CLB Timer
        11. 26.7.1.11 CLB Timer Two States
        12. 26.7.1.12 CLB Interrupt Tag
        13. 26.7.1.13 CLB Output Intersect
        14. 26.7.1.14 CLB PUSH PULL
        15. 26.7.1.15 CLB Multi Tile
        16. 26.7.1.16 CLB Tile to Tile Delay
        17. 26.7.1.17 CLB based One-shot PWM
        18. 26.7.1.18 CLB Trip Zone Timestamp
    8. 26.8 CLB Registers
      1. 26.8.1 CLB Base Addresses
      2. 26.8.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 26.8.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 26.8.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 26.8.5 CLB Registers to Driverlib Functions
  29. 27Revision History

3.17.10 DEV_CFG_REGS Registers

Table 3-98 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-98 should be considered as reserved locations and the register contents should not be modified.

Table 3-98 DEV_CFG_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hDEVCFGLOCK1Lock bit for CPUSELx registersEALLOWGo
8hPARTIDLLower 32-bit of Device PART Identification NumberGo
AhPARTIDHUpper 32-bit of Device PART Identification NumberGo
ChREVIDDevice Revision NumberGo
10hDC0Device Capability: Device InformationGo
12hDC1Device Capability: Processing Block CustomizationGo
14hDC2Device Capability: EMIF CustomizationGo
16hDC3Device Capability: Peripheral CustomizationGo
18hDC4Device Capability: Peripheral CustomizationGo
1AhDC5Device Capability: Peripheral CustomizationGo
1ChDC6Device Capability: Peripheral CustomizationGo
1EhDC7Device Capability: Peripheral CustomizationGo
20hDC8Device Capability: Peripheral CustomizationGo
22hDC9Device Capability: Peripheral CustomizationGo
24hDC10Device Capability: Peripheral CustomizationGo
26hDC11Device Capability: Peripheral CustomizationGo
28hDC12Device Capability: Peripheral CustomizationGo
2AhDC13Device Capability: Peripheral CustomizationGo
2ChDC14Device Capability: Analog Modules CustomizationGo
2EhDC15Device Capability: Analog Modules CustomizationGo
32hDC17Device Capability: Analog Modules CustomizationGo
34hDC18Device Capability: CPU1 Lx SRAM CustomizationGo
36hDC19Device Capability: CPU2 Lx SRAM CustomizationGo
38hDC20Device Capability: GSx SRAM CustomizationGo
60hPERCNF1Peripheral Configuration registerGo
74hFUSEERRe-Fuse error Status registerGo
82hSOFTPRES0Processing Block Software Reset registerEALLOWGo
84hSOFTPRES1EMIF Software Reset registerEALLOWGo
86hSOFTPRES2Peripheral Software Reset registerEALLOWGo
88hSOFTPRES3Peripheral Software Reset registerEALLOWGo
8AhSOFTPRES4Peripheral Software Reset registerEALLOWGo
8EhSOFTPRES6Peripheral Software Reset registerEALLOWGo
90hSOFTPRES7Peripheral Software Reset registerEALLOWGo
92hSOFTPRES8Peripheral Software Reset registerEALLOWGo
94hSOFTPRES9Peripheral Software Reset registerEALLOWGo
98hSOFTPRES11Peripheral Software Reset registerEALLOWGo
9ChSOFTPRES13Peripheral Software Reset registerEALLOWGo
9EhSOFTPRES14Peripheral Software Reset registerEALLOWGo
A2hSOFTPRES16Peripheral Software Reset registerEALLOWGo
D6hCPUSEL0CPU Select register for common peripheralsEALLOWGo
D8hCPUSEL1CPU Select register for common peripheralsEALLOWGo
DAhCPUSEL2CPU Select register for common peripheralsEALLOWGo
DChCPUSEL3CPU Select register for common peripheralsEALLOWGo
DEhCPUSEL4CPU Select register for common peripheralsEALLOWGo
E0hCPUSEL5CPU Select register for common peripheralsEALLOWGo
E2hCPUSEL6CPU Select register for common peripheralsEALLOWGo
E4hCPUSEL7CPU Select register for common peripheralsEALLOWGo
E6hCPUSEL8CPU Select register for common peripheralsEALLOWGo
E8hCPUSEL9CPU Select register for common peripheralsEALLOWGo
EChCPUSEL11CPU Select register for common peripheralsEALLOWGo
EEhCPUSEL12CPU Select register for common peripheralsEALLOWGo
F2hCPUSEL14CPU Select register for common peripheralsEALLOWGo
122hCPU2RESCTLCPU2 Reset Control RegisterEALLOWGo
124hRSTSTATReset Status register for secondary C28x CPUsGo
125hLPMSTATLPM Status Register for secondary C28x CPUsGo
12ChSYSDBGCTLSystem Debug Control registerEALLOWGo

Complex bit access types are encoded to fit into small table cells. Table 3-99 shows the codes that are used for access types in this section.

Table 3-99 DEV_CFG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1SW
1S		Write
1 to set
WOnceW
Once		Write
Write once
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.17.10.1 DEVCFGLOCK1 Register (Offset = 0h) [Reset = 00000000h]

DEVCFGLOCK1 is shown in Figure 3-87 and described in Table 3-100.

Return to the Summary Table.

Lock bit for CPUSELx registers

The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-87 DEVCFGLOCK1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDCPUSEL14CPUSEL13CPUSEL12CPUSEL11CPUSEL10CPUSEL9CPUSEL8
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
CPUSEL7CPUSEL6CPUSEL5CPUSEL4CPUSEL3CPUSEL2CPUSEL1CPUSEL0
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-100 DEVCFGLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDR-00hReserved
14CPUSEL14R/WSonce0hLock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13CPUSEL13R/WSonce0hLock bit for CPUSEL13 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

12CPUSEL12R/WSonce0hLock bit for CPUSEL12 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11CPUSEL11R/WSonce0hLock bit for CPUSEL11 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

10CPUSEL10R/WSonce0hLock bit for CPUSEL10 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9CPUSEL9R/WSonce0hLock bit for CPUSEL9 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

8CPUSEL8R/WSonce0hLock bit for CPUSEL8 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

7CPUSEL7R/WSonce0hLock bit for CPUSEL7 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

6CPUSEL6R/WSonce0hLock bit for CPUSEL6 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

5CPUSEL5R/WSonce0hLock bit for CPUSEL5 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

4CPUSEL4R/WSonce0hLock bit for CPUSEL4 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3CPUSEL3R/WSonce0hLock bit for CPUSEL3 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

2CPUSEL2R/WSonce0hLock bit for CPUSEL2 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1CPUSEL1R/WSonce0hLock bit for CPUSEL1 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0CPUSEL0R/WSonce0hLock bit for CPUSEL0 register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.17.10.2 PARTIDL Register (Offset = 8h) [Reset = 00000000h]

PARTIDL is shown in Figure 3-88 and described in Table 3-101.

Return to the Summary Table.

Lower 32-bit of Device PART Identification Number

Figure 3-88 PARTIDL Register
3130292827262524
PARTID_FORMAT_REVISIONRESERVED
R-0hR-0h
2322212019181716
FLASH_SIZE
R-0h
15141312111098
RESERVEDINSTASPINRESERVEDRESERVEDPIN_COUNT
R-0hR-0hR-0hR-0hR-0h
76543210
QUALRESERVEDRESERVEDRESERVED
R-0hR-0hR-0hR-0h
Table 3-101 PARTIDL Register Field Descriptions
BitFieldTypeResetDescription
31-28PARTID_FORMAT_REVISIONR0hRevision of the PARTID format

Reset type: XRSn

27-24RESERVEDR0hReserved
23-16FLASH_SIZER0h0x7 - 512KB
0x6 - 256KB

Note: This field shows flash size on CPU1 (see datasheet for flash size available)

Reset type: XRSn

15RESERVEDR0hReserved
14-13INSTASPINR0h0 = Reserved for future
1 = Reserved for future
2 = Reserved for future
3 = NONE

Reset type: XRSn

12RESERVEDR0hReserved
11RESERVEDR0hReserved
10-8PIN_COUNTR0h0 = reserved for future
1 = reserved for future
2 = reserved for future
3 = reserved for future
4 = reserved for future
5 = 100 pin
6 = 176 pin
7 = 337 pin

Reset type: XRSn

7-6QUALR0h0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)

Reset type: XRSn

5RESERVEDR0hReserved
4-3RESERVEDR0hReserved
2-0RESERVEDR0hReserved

3.17.10.3 PARTIDH Register (Offset = Ah) [Reset = 00000000h]

PARTIDH is shown in Figure 3-89 and described in Table 3-102.

Return to the Summary Table.

Upper 32-bit of Device PART Identification Number

Figure 3-89 PARTIDH Register
31302928272625242322212019181716
DEVICE_CLASS_IDPARTNO
R-0hR-0h
1514131211109876543210
FAMILYRESERVED
R-0hR-0h
Table 3-102 PARTIDH Register Field Descriptions
BitFieldTypeResetDescription
31-24DEVICE_CLASS_IDR0hReserved

Reset type: XRSn

23-16PARTNOR0hRefer to Datasheet for Device Part Number

Reset type: XRSn

15-8FAMILYR0hDevice Family
0x3 - DUAL CORE
0x4 - SINGLE CORE
0x5 - PICCOLO SINGLE CORE
Other values Reserved

Reset type: XRSn

7-0RESERVEDR0hReserved

3.17.10.4 REVID Register (Offset = Ch) [Reset = 00000000h]

REVID is shown in Figure 3-90 and described in Table 3-103.

Return to the Summary Table.

Device Revision Number

Figure 3-90 REVID Register
313029282726252423222120191817161514131211109876543210
REVID
R-0h
Table 3-103 REVID Register Field Descriptions
BitFieldTypeResetDescription
31-0REVIDR0hThese 32-bits specify the silicon revision. See your device specific datasheet for details.

Reset type: N/A

3.17.10.5 DC0 Register (Offset = 10h) [Reset = 0000000Xh]

DC0 is shown in Figure 3-91 and described in Table 3-104.

Return to the Summary Table.

Device Capability: Device Information

Figure 3-91 DC0 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSINGLE_CORE
R-0-0hR-X
Table 3-104 DC0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-1RESERVEDR-00hReserved
0SINGLE_CORERXSingle Core vs Dual Core
0: Single Core
1: Dual Core

Reset type: XRSn

3.17.10.6 DC1 Register (Offset = 12h) [Reset = 00000XXXh]

DC1 is shown in Figure 3-92 and described in Table 3-105.

Return to the Summary Table.

Device Capability: Processing Block Customization

Figure 3-92 DC1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDCPU2_CLA1
R-0-0hR-XR-X
76543210
RESERVEDCPU1_CLA1RESERVEDCPU2_VCUCPU1_VCUCPU2_FPU_TMUCPU1_FPU_TMU
R-XR-XR-0-0hR-XR-XR-XR-X
Table 3-105 DC1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-10RESERVEDR-00hReserved
9RESERVEDRXReserved
8CPU2_CLA1RX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

7RESERVEDRXReserved
6CPU1_CLA1RX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

5-4RESERVEDR-00hReserved
3CPU2_VCURX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

2CPU1_VCURX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

1CPU2_FPU_TMURX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

0CPU1_FPU_TMURX0 - feature is not present on this device
1 - feature is present on this device

Reset type: XRSn

3.17.10.7 DC2 Register (Offset = 14h) [Reset = 0000000Xh]

DC2 is shown in Figure 3-93 and described in Table 3-106.

Return to the Summary Table.

Device Capability: EMIF Customization

Figure 3-93 DC2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEMIF2EMIF1
R-0-0hR-XR-X
Table 3-106 DC2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-2RESERVEDR-00hReserved
1EMIF2RXEMIF2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0EMIF1RXEMIF1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.8 DC3 Register (Offset = 16h) [Reset = 0000XXXXh]

DC3 is shown in Figure 3-94 and described in Table 3-107.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-94 DC3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDEPWM12EPWM11EPWM10EPWM9
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-107 DC3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDRXReserved
14RESERVEDRXReserved
13RESERVEDRXReserved
12RESERVEDRXReserved
11EPWM12RXEPWM12 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

10EPWM11RXEPWM11 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

9EPWM10RXEPWM10 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

8EPWM9RXEPWM9 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

7EPWM8RXEPWM8 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

6EPWM7RXEPWM7 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

5EPWM6RXEPWM6 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4EPWM5RXEPWM5 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3EPWM4RXEPWM4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2EPWM3RXEPWM3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1EPWM2RXEPWM2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0EPWM1RXEPWM1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.9 DC4 Register (Offset = 18h) [Reset = 000000XXh]

DC4 is shown in Figure 3-95 and described in Table 3-108.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-95 DC4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDECAP6ECAP5ECAP4ECAP3ECAP2ECAP1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-108 DC4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5ECAP6RXECAP6 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4ECAP5RXECAP5 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3ECAP4RXECAP4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2ECAP3RXECAP3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1ECAP2RXECAP2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0ECAP1RXECAP1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.10 DC5 Register (Offset = 1Ah) [Reset = 0000000Xh]

DC5 is shown in Figure 3-96 and described in Table 3-109.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-96 DC5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDEQEP3EQEP2EQEP1
R-0-0hR-XR-XR-XR-X
Table 3-109 DC5 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDRXReserved
2EQEP3RXEQEP3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1EQEP2RXEQEP2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0EQEP1RXEQEP1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.11 DC6 Register (Offset = 1Ch) [Reset = 000000XXh]

DC6 is shown in Figure 3-97 and described in Table 3-110.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-97 DC6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDCLB4CLB3CLB2CLB1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-110 DC6 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3CLB4RXCLB4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2CLB3RXCLB3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1CLB2RXCLB2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0CLB1RXCLB1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.12 DC7 Register (Offset = 1Eh) [Reset = 000000XXh]

DC7 is shown in Figure 3-98 and described in Table 3-111.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-98 DC7 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSD2SD1
R-0-0hR-XR-XR-XR-XR-XR-XR-XR-X
Table 3-111 DC7 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3RESERVEDRXReserved
2RESERVEDRXReserved
1SD2RXSD2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0SD1RXSD1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.13 DC8 Register (Offset = 20h) [Reset = 0000000Xh]

DC8 is shown in Figure 3-99 and described in Table 3-112.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-99 DC8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSCI_DSCI_CSCI_BSCI_A
R-0-0hR-XR-XR-XR-X
Table 3-112 DC8 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3SCI_DRXSCI_D :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2SCI_CRXSCI_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1SCI_BRXSCI_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0SCI_ARXSCI_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.14 DC9 Register (Offset = 22h) [Reset = 000X000Xh]

DC9 is shown in Figure 3-100 and described in Table 3-113.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-100 DC9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR-XR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSPI_CSPI_BSPI_A
R-0-0hR-XR-XR-XR-X
Table 3-113 DC9 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDRXReserved
16RESERVEDRXReserved
15-4RESERVEDR-00hReserved
3RESERVEDRXReserved
2SPI_CRXSPI_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1SPI_BRXSPI_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0SPI_ARXSPI_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.15 DC10 Register (Offset = 24h) [Reset = 000X000Xh]

DC10 is shown in Figure 3-101 and described in Table 3-114.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-101 DC10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR-XR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2C_BI2C_A
R-0-0hR-XR-X
Table 3-114 DC10 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDRXReserved
16RESERVEDRXReserved
15-2RESERVEDR-00hReserved
1I2C_BRXI2C_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0I2C_ARXI2C_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.16 DC11 Register (Offset = 26h) [Reset = 0000000Xh]

DC11 is shown in Figure 3-102 and described in Table 3-115.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-102 DC11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDCAN_BCAN_A
R-0-0hR-XR-XR-XR-X
Table 3-115 DC11 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDRXReserved
2RESERVEDRXReserved
1CAN_BRXCAN_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0CAN_ARXCAN_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.17 DC12 Register (Offset = 28h) [Reset = 000X000Xh]

DC12 is shown in Figure 3-103 and described in Table 3-116.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-103 DC12 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDUSB_A
R-0-0hR-XR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDMcBSP_BMcBSP_A
R-0-0hR-XR-X
Table 3-116 DC12 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19-18RESERVEDRXReserved
17-16USB_ARXCapability of the USB_A Module:
2'b00: No USB function
2'b01: Device Only
2'b10: Device or Host
2'b11: Device or Host

Reset type: XRSn

15-2RESERVEDR-00hReserved
1McBSP_BRXMcBSP_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0McBSP_ARXMcBSP_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.18 DC13 Register (Offset = 2Ah) [Reset = 0000000Xh]

DC13 is shown in Figure 3-104 and described in Table 3-117.

Return to the Summary Table.

Device Capability: Peripheral Customization

Figure 3-104 DC13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDuPP_A
R-0-0hR-XR-X
Table 3-117 DC13 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-2RESERVEDR-00hReserved
1RESERVEDRXReserved
0uPP_ARXuPP_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.19 DC14 Register (Offset = 2Ch) [Reset = 0000000Xh]

DC14 is shown in Figure 3-105 and described in Table 3-118.

Return to the Summary Table.

Device Capability: Analog Modules Customization

Figure 3-105 DC14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_DADC_CADC_BADC_A
R-0-0hR-XR-XR-XR-X
Table 3-118 DC14 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3ADC_DRXADC_D :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2ADC_CRXADC_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1ADC_BRXADC_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0ADC_ARXADC_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.20 DC15 Register (Offset = 2Eh) [Reset = 000000XXh]

DC15 is shown in Figure 3-106 and described in Table 3-119.

Return to the Summary Table.

Device Capability: Analog Modules Customization

Figure 3-106 DC15 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
CMPSS8CMPSS7CMPSS6CMPSS5CMPSS4CMPSS3CMPSS2CMPSS1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-119 DC15 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7CMPSS8RXCMPSS8 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

6CMPSS7RXCMPSS7 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

5CMPSS6RXCMPSS6 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4CMPSS5RXCMPSS5 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3CMPSS4RXCMPSS4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2CMPSS3RXCMPSS3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1CMPSS2RXCMPSS2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0CMPSS1RXCMPSS1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.21 DC17 Register (Offset = 32h) [Reset = 000X000Xh]

DC17 is shown in Figure 3-107 and described in Table 3-120.

Return to the Summary Table.

Device Capability: Analog Modules Customization

Figure 3-107 DC17 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDDAC_CDAC_BDAC_A
R-0-0hR-XR-XR-XR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR-XR-XR-XR-X
Table 3-120 DC17 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDRXReserved
18DAC_CRXBuffered-DAC_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

17DAC_BRXBuffered-DAC_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

16DAC_ARXBuffered-DAC_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

15-4RESERVEDR-00hReserved
3RESERVEDRXReserved
2RESERVEDRXReserved
1RESERVEDRXReserved
0RESERVEDRXReserved

3.17.10.22 DC18 Register (Offset = 34h) [Reset = 000000XXh]

DC18 is shown in Figure 3-108 and described in Table 3-121.

Return to the Summary Table.

Device Capability: CPU1 Lx SRAM Customization

Figure 3-108 DC18 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDLS5_1LS4_1LS3_1LS2_1LS1_1LS0_1
R-0-0hR-XR-XR-XR-XR-XR-X
Table 3-121 DC18 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-6RESERVEDR-00hReserved
5LS5_1RXLS5_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4LS4_1RXLS4_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3LS3_1RXLS3_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2LS2_1RXLS2_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1LS1_1RXLS1_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0LS0_1RXLS0_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.23 DC19 Register (Offset = 36h) [Reset = 000000XXh]

DC19 is shown in Figure 3-109 and described in Table 3-122.

Return to the Summary Table.

Device Capability: CPU2 Lx SRAM Customization

Figure 3-109 DC19 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDLS5_2LS4_2LS3_2LS2_2LS1_2LS0_2
R-0-0hR-XR-XR-XR-XR-XR-X
Table 3-122 DC19 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-6RESERVEDR-00hReserved
5LS5_2RXLS5_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4LS4_2RXLS4_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3LS3_2RXLS3_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2LS2_2RXLS2_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1LS1_2RXLS1_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0LS0_2RXLS0_2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.24 DC20 Register (Offset = 38h) [Reset = 0000XXXXh]

DC20 is shown in Figure 3-110 and described in Table 3-123.

Return to the Summary Table.

Device Capability: GSx SRAM Customization

Figure 3-110 DC20 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
GS15GS14GS13GS12GS11GS10GS9GS8
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
GS7GS6GS5GS4GS3GS2GS1GS0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-123 DC20 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15GS15RXGS15 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

14GS14RXGS14 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

13GS13RXGS13 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

12GS12RXGS12 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

11GS11RXGS11 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

10GS10RXGS10 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

9GS9RXGS9 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

8GS8RXGS8 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

7GS7RXGS7 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

6GS6RXGS6 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

5GS5RXGS5 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

4GS4RXGS4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3GS3RXGS3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

2GS2RXGS2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

1GS1RXGS1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

0GS0RXGS0 :
0: Feature not present on the device
1: Feature present on the device

Reset type: XRSn

3.17.10.25 PERCNF1 Register (Offset = 60h) [Reset = 000X000Xh]

PERCNF1 is shown in Figure 3-111 and described in Table 3-124.

Return to the Summary Table.

Peripheral Configuration register

Figure 3-111 PERCNF1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDUSB_A_PHY
R-0-0hR-XR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_D_MODEADC_C_MODEADC_B_MODEADC_A_MODE
R-0-0hR-XR-XR-XR-X
Table 3-124 PERCNF1 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDRXReserved
16USB_A_PHYRXInternal PHY is present present or not for the USB_A module:

0: Internal USB PHY Module is not present
1: Internal USB PHY Module is present.

Reset type: XRSn

15-4RESERVEDR-00hReserved
3ADC_D_MODERX 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available

Reset type: XRSn

2ADC_C_MODERX 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available

Reset type: XRSn

1ADC_B_MODERX 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available

Reset type: XRSn

0ADC_A_MODERX 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available

Reset type: XRSn

3.17.10.26 FUSEERR Register (Offset = 74h) [Reset = 00000000h]

FUSEERR is shown in Figure 3-112 and described in Table 3-125.

Return to the Summary Table.

e-Fuse error Status register

Figure 3-112 FUSEERR Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDERRALERR
R-0-0hR-0hR-0h
Table 3-125 FUSEERR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-6RESERVEDR-00hReserved
5ERRR0hEfuse Self Test Error Status set by hardware after fuse self test completes, in case of self test error

0: No error during fuse self test
1: Fuse self test error

Reset type: XRSn

4-0ALERRR0hEfuse Autoload Error Status set by hardware after fuse auto load completes

00000: No error in auto load
Other: Non zero value indicates error in autoload

Reset type: XRSn

3.17.10.27 SOFTPRES0 Register (Offset = 82h) [Reset = 00000000h]

SOFTPRES0 is shown in Figure 3-113 and described in Table 3-126.

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Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-113 SOFTPRES0 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDCPU2_CLA1RESERVEDCPU1_CLA1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-126 SOFTPRES0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2CPU2_CLA1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1RESERVEDR/W0hReserved
0CPU1_CLA1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.28 SOFTPRES1 Register (Offset = 84h) [Reset = 00000000h]

SOFTPRES1 is shown in Figure 3-114 and described in Table 3-127.

Return to the Summary Table.

EMIF Software Reset register

Figure 3-114 SOFTPRES1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEMIF2EMIF1
R-0-0hR/W-0hR/W-0h
Table 3-127 SOFTPRES1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-2RESERVEDR-00hReserved
1EMIF2R/W0hWhen this bit is set, only the control logic of the respective EMIF2 is reset. It does not reset the internal registers except the Total Access register and the Total Activate register.

This bit must be manually cleared after being set.

1: EMIF2 is under SOFTRESET
0: Module reset is determined by the device Reset Network

Reset type: CPU1.SYSRSn

0EMIF1R/W0hWhen this bit is set, only the control logic of the respective EMIF1 is reset. It does not reset the internal registers except the Total Access register and the Total Activate register.

This bit must be manually cleared after being set.

1: EMIF1 is under SOFTRESET
0: Module reset is determined by the device Reset Network

Reset type: CPU1.SYSRSn

3.17.10.29 SOFTPRES2 Register (Offset = 86h) [Reset = 00000000h]

SOFTPRES2 is shown in Figure 3-115 and described in Table 3-128.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-115 SOFTPRES2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDEPWM12EPWM11EPWM10EPWM9
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-128 SOFTPRES2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11EPWM12R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

10EPWM11R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

9EPWM10R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

8EPWM9R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

7EPWM8R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

6EPWM7R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

5EPWM6R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

4EPWM5R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3EPWM4R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

2EPWM3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1EPWM2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0EPWM1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.30 SOFTPRES3 Register (Offset = 88h) [Reset = 00000000h]

SOFTPRES3 is shown in Figure 3-116 and described in Table 3-129.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-116 SOFTPRES3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDECAP6ECAP5ECAP4ECAP3ECAP2ECAP1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-129 SOFTPRES3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5ECAP6R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

4ECAP5R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3ECAP4R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

2ECAP3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1ECAP2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0ECAP1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.31 SOFTPRES4 Register (Offset = 8Ah) [Reset = 00000000h]

SOFTPRES4 is shown in Figure 3-117 and described in Table 3-130.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-117 SOFTPRES4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDEQEP3EQEP2EQEP1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-130 SOFTPRES4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2EQEP3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1EQEP2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0EQEP1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.32 SOFTPRES6 Register (Offset = 8Eh) [Reset = 00000000h]

SOFTPRES6 is shown in Figure 3-118 and described in Table 3-131.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-118 SOFTPRES6 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSD2SD1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-131 SOFTPRES6 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SD2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0SD1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.33 SOFTPRES7 Register (Offset = 90h) [Reset = 00000000h]

SOFTPRES7 is shown in Figure 3-119 and described in Table 3-132.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-119 SOFTPRES7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSCI_DSCI_CSCI_BSCI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-132 SOFTPRES7 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3SCI_DR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

2SCI_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1SCI_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0SCI_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.34 SOFTPRES8 Register (Offset = 92h) [Reset = 00000000h]

SOFTPRES8 is shown in Figure 3-120 and described in Table 3-133.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-120 SOFTPRES8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSPI_CSPI_BSPI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-133 SOFTPRES8 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2SPI_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1SPI_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0SPI_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.35 SOFTPRES9 Register (Offset = 94h) [Reset = 00000000h]

SOFTPRES9 is shown in Figure 3-121 and described in Table 3-134.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-121 SOFTPRES9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2C_BI2C_A
R-0-0hR/W-0hR/W-0h
Table 3-134 SOFTPRES9 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-2RESERVEDR-00hReserved
1I2C_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0I2C_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.36 SOFTPRES11 Register (Offset = 98h) [Reset = 00000000h]

SOFTPRES11 is shown in Figure 3-122 and described in Table 3-135.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-122 SOFTPRES11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDUSB_A
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDMcBSP_BMcBSP_A
R-0-0hR/W-0hR/W-0h
Table 3-135 SOFTPRES11 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16USB_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

15-2RESERVEDR-00hReserved
1McBSP_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0McBSP_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.37 SOFTPRES13 Register (Offset = 9Ch) [Reset = 00000000h]

SOFTPRES13 is shown in Figure 3-123 and described in Table 3-136.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-123 SOFTPRES13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_DADC_CADC_BADC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-136 SOFTPRES13 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3ADC_DR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

2ADC_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1ADC_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0ADC_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.38 SOFTPRES14 Register (Offset = 9Eh) [Reset = 00000000h]

SOFTPRES14 is shown in Figure 3-124 and described in Table 3-137.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-124 SOFTPRES14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
CMPSS8CMPSS7CMPSS6CMPSS5CMPSS4CMPSS3CMPSS2CMPSS1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-137 SOFTPRES14 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7CMPSS8R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

6CMPSS7R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

5CMPSS6R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

4CMPSS5R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3CMPSS4R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

2CMPSS3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

1CMPSS2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

0CMPSS1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

3.17.10.39 SOFTPRES16 Register (Offset = A2h) [Reset = 00000000h]

SOFTPRES16 is shown in Figure 3-125 and described in Table 3-138.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-125 SOFTPRES16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDDAC_CDAC_BDAC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-138 SOFTPRES16 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18DAC_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

17DAC_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

16DAC_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: CPU1.SYSRSn

15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.17.10.40 CPUSEL0 Register (Offset = D6h) [Reset = 00000000h]

CPUSEL0 is shown in Figure 3-126 and described in Table 3-139.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-126 CPUSEL0 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDEPWM12EPWM11EPWM10EPWM9
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-139 CPUSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11EPWM12R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

10EPWM11R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

9EPWM10R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

8EPWM9R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

7EPWM8R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

6EPWM7R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

5EPWM6R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

4EPWM5R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3EPWM4R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

2EPWM3R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1EPWM2R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0EPWM1R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.41 CPUSEL1 Register (Offset = D8h) [Reset = 00000000h]

CPUSEL1 is shown in Figure 3-127 and described in Table 3-140.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-127 CPUSEL1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDECAP6ECAP5ECAP4ECAP3ECAP2ECAP1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-140 CPUSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5ECAP6R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

4ECAP5R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3ECAP4R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

2ECAP3R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1ECAP2R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0ECAP1R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.42 CPUSEL2 Register (Offset = DAh) [Reset = 00000000h]

CPUSEL2 is shown in Figure 3-128 and described in Table 3-141.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-128 CPUSEL2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDEQEP3EQEP2EQEP1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-141 CPUSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2EQEP3R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1EQEP2R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0EQEP1R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.43 CPUSEL3 Register (Offset = DCh) [Reset = 00000000h]

CPUSEL3 is shown in Figure 3-129 and described in Table 3-142.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-129 CPUSEL3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-142 CPUSEL3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.17.10.44 CPUSEL4 Register (Offset = DEh) [Reset = 00000000h]

CPUSEL4 is shown in Figure 3-130 and described in Table 3-143.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-130 CPUSEL4 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSD2SD1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-143 CPUSEL4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SD2R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0SD1R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.45 CPUSEL5 Register (Offset = E0h) [Reset = 00000000h]

CPUSEL5 is shown in Figure 3-131 and described in Table 3-144.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-131 CPUSEL5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSCI_DSCI_CSCI_BSCI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-144 CPUSEL5 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3SCI_DR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

2SCI_CR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1SCI_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0SCI_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.46 CPUSEL6 Register (Offset = E2h) [Reset = 00000000h]

CPUSEL6 is shown in Figure 3-132 and described in Table 3-145.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-132 CPUSEL6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSPI_CSPI_BSPI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-145 CPUSEL6 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2SPI_CR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1SPI_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0SPI_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.47 CPUSEL7 Register (Offset = E4h) [Reset = 00000000h]

CPUSEL7 is shown in Figure 3-133 and described in Table 3-146.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-133 CPUSEL7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2C_BI2C_A
R-0-0hR/W-0hR/W-0h
Table 3-146 CPUSEL7 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-2RESERVEDR-00hReserved
1I2C_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0I2C_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.48 CPUSEL8 Register (Offset = E6h) [Reset = 00000000h]

CPUSEL8 is shown in Figure 3-134 and described in Table 3-147.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-134 CPUSEL8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDCAN_BCAN_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-147 CPUSEL8 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1CAN_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0CAN_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.49 CPUSEL9 Register (Offset = E8h) [Reset = 00000000h]

CPUSEL9 is shown in Figure 3-135 and described in Table 3-148.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-135 CPUSEL9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDMcBSP_BMcBSP_A
R-0-0hR/W-0hR/W-0h
Table 3-148 CPUSEL9 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-2RESERVEDR-00hReserved
1McBSP_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0McBSP_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.50 CPUSEL11 Register (Offset = ECh) [Reset = 00000000h]

CPUSEL11 is shown in Figure 3-136 and described in Table 3-149.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-136 CPUSEL11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_DADC_CADC_BADC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-149 CPUSEL11 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-4RESERVEDR-00hReserved
3ADC_DR/W0h0: Connected to CPU1
1: Connected to CPU2

Note:
[1] These CPUSEL bits affect the ownership of only ADC Configuration registers by CPU1 or CPU2 (which are mapped on the mapped to VBUS32). ADC result registers are readable from all masters without any CPUSEL dependency.

Reset type: CPU1.SYSRSn

2ADC_CR/W0h0: Connected to CPU1
1: Connected to CPU2

Note:
[1] These CPUSEL bits affect the ownership of only ADC Configuration registers by CPU1 or CPU2 (which are mapped on the mapped to VBUS32). ADC result registers are readable from all masters without any CPUSEL dependency.

Reset type: CPU1.SYSRSn

1ADC_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Note:
[1] These CPUSEL bits affect the ownership of only ADC Configuration registers by CPU1 or CPU2 (which are mapped on the mapped to VBUS32). ADC result registers are readable from all masters without any CPUSEL dependency.

Reset type: CPU1.SYSRSn

0ADC_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Note:
[1] These CPUSEL bits affect the ownership of only ADC Configuration registers by CPU1 or CPU2 (which are mapped on the mapped to VBUS32). ADC result registers are readable from all masters without any CPUSEL dependency.

Reset type: CPU1.SYSRSn

3.17.10.51 CPUSEL12 Register (Offset = EEh) [Reset = 00000000h]

CPUSEL12 is shown in Figure 3-137 and described in Table 3-150.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-137 CPUSEL12 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
CMPSS8CMPSS7CMPSS6CMPSS5CMPSS4CMPSS3CMPSS2CMPSS1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-150 CPUSEL12 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8RESERVEDR-00hReserved
7CMPSS8R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

6CMPSS7R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

5CMPSS6R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

4CMPSS5R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3CMPSS4R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

2CMPSS3R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

1CMPSS2R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

0CMPSS1R/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

3.17.10.52 CPUSEL14 Register (Offset = F2h) [Reset = 00000000h]

CPUSEL14 is shown in Figure 3-138 and described in Table 3-151.

Return to the Summary Table.

CPU Select register for common peripherals

This register must be configured prior to enabling the peripheral clocks.

The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.

The reset for each peripheral is also driven from the selected CPU.

Figure 3-138 CPUSEL14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDDAC_CDAC_BDAC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-151 CPUSEL14 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18DAC_CR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

17DAC_BR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

16DAC_AR/W0h0: Connected to CPU1
1: Connected to CPU2

Reset type: CPU1.SYSRSn

15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.17.10.53 CPU2RESCTL Register (Offset = 122h) [Reset = 00000001h]

CPU2RESCTL is shown in Figure 3-139 and described in Table 3-152.

Return to the Summary Table.

CPU2 Reset Control Register

Figure 3-139 CPU2RESCTL Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESET
R-0-0hR/W-1h
Table 3-152 CPU2RESCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to this register succeeds only if this field is written with a value of 0xa5a5

Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored

Reset type: N/A

15-1RESERVEDR-00hReserved
0RESETR/W1hThis bit controls the reset input of CPU2 core.

1: CPU2 is held in reset (CPU2.RSn = 0)
0: CPU2 reset is deactivated (CPU2.RSn = 1)

Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put CPU2 in STANDBY mode rather than in reset to save on active power component on the CPU2 subsystem. This is because, all clocks keep toggling when reset is active on the CPU2 sub-system.

[2] Note: If CPU2 is in Standby mode, writing to this bit will have no effect. CPU2 may be reset by any Chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn) or HIBRESETn. Alternately CPU2 may be woken up by any configured wake-up event.

Reset type: CPU1.SYSRSn

3.17.10.54 RSTSTAT Register (Offset = 124h) [Reset = 0000h]

RSTSTAT is shown in Figure 3-140 and described in Table 3-153.

Return to the Summary Table.

Reset Status register for secondary C28x CPUs

Figure 3-140 RSTSTAT Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCPU2HWBISTRST1CPU2HWBISTRST0CPU2NMIWDRSTCPU2RES
R-0-0hR/W1S-0hR/W1S-0hR/W1S-0hR-0h
Table 3-153 RSTSTAT Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR-00hReserved
3CPU2HWBISTRST1R/W1S0hCPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates whether a HWBIST reset was issued to CPU2 or not

00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset

This status bit is a latched flag. This flag can be cleared by the CPU1 by writing a 1

Reset type: CPU1.SYSRSn

2CPU2HWBISTRST0R/W1S0hCPU2HWBISTRST0 and CPU2HWBISTRST1 together indicates whether a HWBIST reset was issued to CPU2 or not

00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset

This status bit is a latched flag. This flag can be cleared by the CPU1 by writing a 1

Reset type: CPU1.SYSRSn

1CPU2NMIWDRSTR/W1S0hIndicates whether a CPU2.NMIWD reset was issued to CPU2 or not

0: CPU2 was not reset by the CPU2.NMIWD
1: CPU2 was reset due to CPU2.NMIWD reset

This status bit is a latched flag.This flag can be cleared by the CPU1 by writing a 1

Reset type: CPU1.SYSRSn

0CPU2RESR0hReset status of CPU2 to CPU1

0: CPU2 core is in reset
1: CPU2 core is out of reset

Reset type: CPU1.SYSRSn

3.17.10.55 LPMSTAT Register (Offset = 125h) [Reset = 0000h]

LPMSTAT is shown in Figure 3-141 and described in Table 3-154.

Return to the Summary Table.

LPM Status Register for secondary C28x CPUs

Figure 3-141 LPMSTAT Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCPU2LPMSTAT
R-0-0hR-0h
Table 3-154 LPMSTAT Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR-00hReserved
1-0CPU2LPMSTATR0hThese bits indicate the power mode CPU2

00: CPU2 is in ACTIVE mode
01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved

Reset type: CPU1.SYSRSn

3.17.10.56 SYSDBGCTL Register (Offset = 12Ch) [Reset = 00000000h]

SYSDBGCTL is shown in Figure 3-142 and described in Table 3-155.

Return to the Summary Table.

System Debug Control register

Figure 3-142 SYSDBGCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDBIT_0
R-0-0hR/W-0h
Table 3-155 SYSDBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-1RESERVEDR-00hReserved
0BIT_0R/W0hThis bit is for use in PLL startup and is only reset by POR.

Reset type: POR