SPRUI97E May   2017  – September 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Device Information
  6. 2AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware
    1. 2.1  Functional Description
      1. 2.1.1 Processor
      2. 2.1.2 Clocks
      3. 2.1.3 Reset Signals
    2. 2.2  Power Supplies
      1. 2.2.1 Power Source
      2. 2.2.2 TPS6590377 PMIC
      3. 2.2.3 AVS Control
      4. 2.2.4 Other Power Supplies
    3. 2.3  Configuration/Setup
      1. 2.3.1 Boot Configuration
      2. 2.3.2 I2C Address Assignments
      3. 2.3.3 SEEPROM Header
      4. 2.3.4 JTAG Emulation
    4. 2.4  Memories Supported
      1. 2.4.1 DDR3L SDRAM
      2. 2.4.2 SPI NOR Flash
      3. 2.4.3 Board Identity Memory
      4. 2.4.4 SD/MMC
      5. 2.4.5 eMMC NAND Flash
    5. 2.5  Ethernet Ports
      1. 2.5.1 100Mb Ethernet Ports on PRU-ICSS
      2. 2.5.2 Gigabit (1000Mb) Ethernet Ports
    6. 2.6  USB Ports
      1. 2.6.1 Processor USB Port 1
      2. 2.6.2 Processor USB Port 2
      3. 2.6.3 FTDI USB Port
    7. 2.7  PCIe
    8. 2.8  Video Input and Output
      1. 2.8.1 Camera
      2. 2.8.2 HDMI
      3. 2.8.3 LCD
    9. 2.9  Industrial Interfaces
      1. 2.9.1 Profibus
      2. 2.9.2 DCAN
      3. 2.9.3 RS-485
    10. 2.10 User Interfaces
      1. 2.10.1 Tri-Color LEDs
      2. 2.10.2 Industrial Inputs
      3. 2.10.3 Industrial Outputs / LEDs
    11. 2.11 Pin Use Description
      1. 2.11.1 Functional Interface Mapping
      2. 2.11.2 GPIO Pin Mapping
    12. 2.12 Board Connectors
  7. 3Additional Information
    1. 3.1 Known Deficiencies in AM571x IDK EVM
      1. 3.1.1  Power solution not sufficient for full PCIe plug-in card compliance
      2. 3.1.2  Early versions of the AM571x IDK EVM not installed with SOC devices rated for the full industrial temperature range
      3. 3.1.3  AM571x IDK EVM does not support eMMC HS200 mode
      4. 3.1.4  PCIe PERSTn line not in proper state at start-up
      5. 3.1.5  EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and PRU2
      6. 3.1.6  HDQ implementation not correct
      7. 3.1.7  Removing the power plug and inserting it again while the power supply is energized can cause damage
      8. 3.1.8  Software shutdown of PMIC not operational
      9. 3.1.9  CCS System Reset fails
      10. 3.1.10 AM571x IDK EVM design contains two clamp circuits that may not be necessary
      11. 3.1.11 Crystal connected to osc0 needs to have 50ppm or better long term accuracy
      12. 3.1.12 Software must program the CDCE913 for 0pf load capacitance
      13. 3.1.13 Protection diode D2 should be rated for 5V
      14. 3.1.14 PHY address LSB for U9 and U15 can be latched incorrectly
      15. 3.1.15 3.3-V clamp circuit needs more margin
      16. 3.1.16 Current PMIC does not provide the mandated power down sequence
      17. 3.1.17 Power supply droop may cause board reset
      18. 3.1.18 AM5718 pin N21 must be connected to 1.8 V, as it is VDDS18V_DDR1 and not N/C
      19. 3.1.19 VOUT1 is used at 3.3 V, which violates erratum i920
      20. 3.1.20 PMIC OSC16MCAP pin mistakenly grounded
    2. 3.2 Trademarks
    3.     76
  8. 4Revision History

2.5.2 Gigabit (1000Mb) Ethernet Ports

The AM571x IDK EVM contains two Gigabit (1000Mb) Ethernet PHY/Transceivers (KSZ9031RN) interfaced to connectors J10 (RGMII0) and J12 (RGMII1). These Gigabit Ethernet transceivers are connected over RGMII0 and RGMII1 to the Ethernet switch block within the AM5718 processor.

The resets for the transceivers are driven low coincident with the PORz reset to the AM5718 processor. A 25-MHz clock is provided into each of the KSZ9031RN Gigabit transceivers.