SPRUJ63A September   2022  – October 2023

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
    2. 1.2 Inside the Box
  4. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
    2. 2.2 EMC, EMI, and ESD Compliance
  5. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  6. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
    3. 4.3 Issue 3 - uSD Card Boot Not Working
  7. 5References
  8. 6Revision History

Test Automation

A Test automation header J38 is provided to allow an external controller to control the power on/off, boot modes, reset functionality and current measurement to support automated testing. The test automation header includes four GPIOs, two I2C interfaces. The basic controls as shown in Table 3-16.

Table 3-16 List of Signals Routed to Test Automation Header
SignalSignal TypeFunction
POWER_DOWNGPIOInstructs the EVM to power down all circuits
PORGPIOCreates a PORz into the AM64x SoC
WARM_RESETGPIOCreates a RESETz into the AM64x SoC
GPIO1GPIOGPIO for communication with AM64x SoC
GPIO2GPIOConnected to I2C IO Expander
GPIO3GPIOUsed to Enable the BOOTMODE Buffer
GPIO4GPIOUsed to Reset the Boot mode IO Expander
I2C0I2CCommunicates with Boot mode I2C buffer
I2C2I2CCommunicates with INA226 current measurement devices

One of the I2C interface from Test automation header is connected to an I2C IO expander, which can drive the Boot mode pins of the processor.

Note: The bootmode selection switches are in the OFF condition and GPIO3 are set to logic low to enable this mode.

The other I2C interface is connected to the current measurement and temperature sensing devices present on the I2C1 port of the SoC.

The Test Automation connector is used by Texas Instruments for control of software regression testing and comparative power measurements. The connector is provided to allow customers to develop their own testing and power measurements of customer applications.

Note: The power measurements are not a substitute for the AM64x/AM243x Power Estimation Tool and is not used for the design of power supply solutions.

Power measurements varies based on silicon process and environment and measurements can only used for comparison with other measurements taken on the same EVM.

GUID-039CFDD6-804E-4422-ADFC-522043F784FE-low.pngFigure 3-12 Test Automation Header
Table 3-17 Test Automation Header (J38) Pin-out
Pin No.SignalIO Direction (to CP board)
1VCC3V3_1Power (out)
2VCC3V3_1Power (out)
3VCC3V3_1Power (out)
4NCNA
5NCNA
6NCNA
7DGNDGround
8NCNA
9NCNA
10NCNA
11NCNA
12NCNA
13NCNA
14NCNA
15NCNA
16DGNDGround
17NCNA
18NCNA
19NCNA
20NCNA
21NCNA
22NCNA
23NCNA
24NCNA
25DGNDGround
26TEST_POWERDOWNInput
27TEST_PORzInput
28TEST_WARMRESETnInput
29NCNA
30TEST_GPIO1Bidirectional
31TEST_GPIO2Bidirectional
32TEST_GPIO3Input
33TEST_GPIO4Input
34DGNDGround
35NCNA
36SOC_I2C1_SCLBidirectional
37BOOTMODE_I2C_SCLBidirectional
38SOC_I2C1_SDABidirectional
39BOOTMODE_I2C_SDABidirectional
40DGNDGround
41DGNDGround
42DGNDGround