SPRUJF0 August   2025 F28E120SB , F28E120SC , TMS320F2802-Q1 , TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F280220 , TMS320F28023 , TMS320F28023-Q1 , TMS320F280230 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F280270 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-EP , TMS320F28035-Q1

 

  1.   1
  2.   TMS320F2802x/TMS320F2803x to TMS320F28E12x Migration Overview
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Abbreviations
  5. 2 Central Processing Unit (CPU)
  6. 3 Development Tools
    1. 3.1 Driver Library (Driverlib)
    2. 3.2 Migrating Between IQ_Math and Native Floating-Point
    3. 3.3 Embedded Application Binary Interface (EABI) Support
  7. 4 Package and Pinout
  8. 5 Operating Frequency and Power Management
  9. 6 Power Sequencing
  10. 7 Memory Map
    1. 7.1 Random Access Memory (RAM)
    2. 7.2 Flash and OTP
      1. 7.2.1 Size and Number of Sectors
      2. 7.2.2 Flash Parameters
      3. 7.2.3 Entry Point into Flash
      4. 7.2.4 Dual Code Security Module (DCSM) and Password Locations
      5. 7.2.5 OTP
      6. 7.2.6 Flash Programming
    3. 7.3 Boot ROM
      1. 7.3.1 Boot ROM Reserved RAM
      2. 7.3.2 Boot Mode Selection
      3. 7.3.3 Bootloaders
  11. 8 Architectural Enhancements
    1. 8.1 Clock Sources and Domains
    2. 8.2 Dual-Clock Comparator (DCC) Module
    3. 8.3 Watchdog Timer
    4. 8.4 Peripheral Interrupt Expansion (PIE)
    5. 8.5 Lock Protection Registers
    6. 8.6 General-Purpose Input/Output (GPIO)
    7. 8.7 External Interrupts
    8. 8.8 Crossbar (X-BAR)
  12. 9 Peripherals
    1. 9.1 New Peripherals
      1. 9.1.1 Direct Memory Access (DMA)
      2. 9.1.2 Analog Subsystem Interconnect
      3. 9.1.3 Comparator Subsystem (CMPSS)
      4. 9.1.4 Programmable Gain Amplifier (PGA)
    2. 9.2 Control Peripherals
      1. 9.2.1 Enhanced Pulse Width Modulator (MCPWM)
      2. 9.2.2 Enhanced Capture Module (eCAP)
      3. 9.2.3 Enhanced Quadrature Encode Pulse Module (eQEP)
    3. 9.3 Analog Peripherals
      1. 9.3.1 Analog-to-Digital Converter (ADC)
    4. 9.4 Communication Peripherals
      1. 9.4.1 SPI
      2. 9.4.2 SCI
      3. 9.4.3 UART
      4. 9.4.4 I2C
  13. 10Emulation – JTAG Port
  14. 11Silicon Errata
  15. 12Device Comparison Summary
  16. 13References

7.2.1 Size and Number of Sectors

The size and number of sectors has changed and code must be rebuilt accordingly. The exact flash size as well as sector configuration varies from device to device. For details, see Table 7-2. Note that code to program the flash can be executed out of RAM and there cannot be any kind of access to the flash bank when an erase or program operation is in progress.

Table 7-2 Flash Sector Configuration by Device
F280200 F28026
F28022
F28020		 F28027
F28023
F28021		 F28030 F28033
F28032
F28031		 F28035
F28034		 F28E120SC F28E120SB
Sectors 2 4 4 4 8 8 64 32
Size 4K x 16 4K x 16 8K x 16 4K x 16 4K x 16 8K x 16 64K x 16 32K x 16
Total 8K x 16 16K x 16 32K x 16 16K x 16 32K x 16 64K x 16 64K x 16 32K x 16