SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

11.7 SD-HOST Registers

Table 11-4 lists the memory-mapped registers for the SD-HOST. All register offset addresses not listed in Table 11-4 should be considered as reserved locations and the register contents should not be modified.

Table 11-3 Base Address of SD-Host (also referred as MMCHS)
Module NameBase Address
MMCHS10x4401 0000
Table 11-4 SD-HOST Registers
OffsetAcronymRegister NameSection
124hMMCHS_CSRECard Status Response ErrorSection 11.7.1
12ChMMCHS_CONConfigurationSection 11.7.2
204hMMCHS_BLKTransfer Length ConfigurationSection 11.7.3
208hMMCHS_ARGCommand ArgumentSection 11.7.4
20ChMMCHS_CMDCommand and Transfer ModeSection 11.7.5
210hMMCHS_RSP10Command Response[31:0]Section 11.7.6
214hMMCHS_RSP32Command Response[63:32]Section 11.7.7
218hMMCHS_RSP54Command Response[95:64]Section 11.7.8
21ChMMCHS_RSP76Command Response[127:96]Section 11.7.9
220hMMCHS_DATADataSection 11.7.10
224hMMCHS_PSTATEPresent StateSection 11.7.11
228hMMCHS_HCTLControlSection 11.7.12
22ChMMCHS_SYSCTLSD System ControlSection 11.7.13
230hMMCHS_STATInterrupt StatusSection 11.7.14
234hMMCHS_IEInterrupt SD EnableSection 11.7.15
238hMMCHS_ISEInterrupt Signal EnableSection 11.7.16

11.7.1 MMCHS_CSRE Register (Offset = 124h) [reset = 0h]

Card Status Response Error register

MMCHS_CSRE is shown in Figure 11-2 and described in Table 11-5.

Return to Summary Table.

This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO.

When a bit MMCi.MMCHS_CSRE[I] is set to 1, if the corresponding bit at the same position in the response MMCi.MMCHS_RSP10[I] is set to 1, the host controller indicates a card error (MMCi.MMCHS_STAT[28] CERR bit) interrupt status to avoid the host driver reading the response register (MMCi.MMCHS_RSP10).

Note:

No automatic card error detection for autoCMD12 is implemented; the host system must check autoCMD12 response register (MMCi.MMCHS_RSP76) for possible card errors.

Figure 11-2 MMCHS_CSRE Register
313029282726252423222120191817161514131211109876543210
CSRE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-5 MMCHS_CSRE Register Field Descriptions
BitFieldTypeResetDescription
31-0CSRER/W0h

Card status response error

11.7.2 MMCHS_CON Register (Offset = 12Ch) [reset = 0h]

Configuration register

MMCHS_CON is shown in Figure 11-3 and described in Table 11-6.

Return to Summary Table.

This register is used to do the following:

  • Select the functional mode for any card
  • Send an initialization sequence to any card
  • Enable the detection on the mmci_dat[1] signal of a card interrupt for SDIO cards only
  • Configure specific data and command transfers for MMC cards only
  • Configure the parameters related to the card detect and write protect input signals.

Figure 11-3 MMCHS_CON Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHRINITRESERVED
R-0hR/W-0hR/W-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-6 MMCHS_CON Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2HRR/W0h

Broadcast host response (only for MMC cards)

This register is used to force the host to generate a 48-bit response for bc command type.

It can be used to terminate the interrupt mode by generating a CMD40 response by the core. To have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1.

When MMCi.MMCHS_CON[12] CEATA bit is set to 1 and MMCi.MMCHS_ARG set to 0x00000000, when writing 0x00000000 into MMCi.MMCHS_CMD register, the host controller performs a 'command completion signal disable' token (such as mmci_cmd line held to 0 during 47 cycles followed by a 1).

1INITR/W0h

Send initialization stream (all cards)

When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card.

An initialization sequence consists of setting the mmci_cmd line to 1 during 80 clock cycles. The initialization sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCi.MMCHS_SYSCTL[15:6] CLKD bits) should be set to ensure that 80 clock periods are greater than 1ms.

Note: in this mode, there is no command sent to the card and no response is expected. A command complete interrupt will be generated once the initialization sequence is completed. MMCi.MMCHS_STAT[0] CC bit can be polled.

0h = The host does not send an initialization sequence.

1h = The host sends an initialization sequence.

0RESERVEDR0h

11.7.3 MMCHS_BLK Register (Offset = 204h) [reset = 0h]

Transfer Length Configuration register

MMCHS_BLK is shown in Figure 11-4 and described in Table 11-7.

Return to Summary Table.

This register shall be used for any card.

Figure 11-4 MMCHS_BLK Register
31302928272625242322212019181716
NBLK
R/W-0h
1514131211109876543210
RESERVEDBLEN
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-7 MMCHS_BLK Register Field Descriptions
BitFieldTypeResetDescription
31-16NBLKR/W0h

Blocks count for current transfer

This register is enabled when the Block count Enable (MMCi.MMCHS_CMD[1] BCE bit) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (such as after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count.

0h = Stop count

1h = 1 block

2h = 2 blocks

FFFFh = 65535 blocks

15-11RESERVEDR0h
10-0BLENR/W0h

Transfer Block Size

This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCi.MMCHS_STAT[1] TC bit set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched.

0h = No data transfer

1h = 1 byte block length

2h = 2 bytes block length

3h = 3 bytes block length

1FFh = 511 bytes block length

200h = 512 bytes block length

3FFh = 1023 bytes block length

400h = 1024 bytes block length

11.7.4 MMCHS_ARG Register (Offset = 208h) [reset = 0h]

Command Argument register

MMCHS_ARG is shown in Figure 11-5 and described in Table 11-8.

Return to Summary Table.

This register contains a command argument specified as bit 39-8 of Command-Format.

These registers must be initialized prior to sending the command to the card (write action into the register MMCi.MMCHS_CMD register). The only exception is for a command index specifying stuff bits in arguments, making a write unnecessary.

Figure 11-5 MMCHS_ARG Register
313029282726252423222120191817161514131211109876543210
ARG
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-8 MMCHS_ARG Register Field Descriptions
BitFieldTypeResetDescription
31-0ARGR/W0h

Command argument bits [31:0]

For CMD52, ARG must be programmed with IO_RW_DIRECT[39:8]. Refer to SDIO specification.

11.7.5 MMCHS_CMD Register (Offset = 20Ch) [reset = 0h]

Command and Transfer Mode register

MMCHS_CMD is shown in Figure 11-6 and described in Table 11-9.

Return to Summary Table.

MMCi.MMCHS_CMD[31:16] = the command register

MMCi.MMCHS_CMD[15:0] = the transfer mode.

This register configures the data and command transfers. A write into the most significant byte sends the command. A write into MMCi.MMCHS_CMD[15:0] registers during data transfer has no effect. This register shall be used for any card.

Figure 11-6 MMCHS_CMD Register
3130292827262524
RESERVEDINDX
R-0hR/W-0h
2322212019181716
CMD_TYPEDPCICECCCERESERVEDRSP_TYPE
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMSBSDDIRRESERVEDBCEDE
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-9 MMCHS_CMD Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h
29-24INDXR/W0h

Command index

Binary-encoded value from 0 to 63, specifying the command number send to card.

0h = CMD0 or ACMD0

1h = CMD1 or ACMD1 3Fh = CMD63 or ACMD63

23-22CMD_TYPER/W0h

Command type

This register specifies three types of special commands: Suspend, Resume, and Abort. These bits shall be set to 0b00 for all other commands.

0h = Other commands

1h = Upon CMD52 Bus Suspend operation

2h = Upon CMD52 Function Select operation

3h = Upon CMD12 or CMD52 I/O Abort command

21DPR/W0h

Data present select

This register indicates that data is present, and mmci_dat line shall be used. It must be set to 0 in the following conditions: Command using only mmci_cmd line Command with no data transfer, but using busy signal on mmci_dat[0] Resume command

0h = Command with no data transfer

1h = Command with data transfer

20CICER/W0h

Command Index check enable

This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it is reported as a command index error (MMCi.MMCHS_STAT[19] CIE bit set to1)

Note: The CICE bit cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued.

0h = Index check disable

1h = Index check enable

19CCCER/W0h

Command CRC check enable

This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC error (MMCi.MMCHS_STAT[17] CCRC bit set to 1).

Note: The CCCE bit cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued.

0h = CRC7 check disable

1h = CRC7 check enable

18RESERVEDR0h
17-16RSP_TYPER/W0h

Response type

These bits define the response type of the command.

0h = No response

1h = Response Length 136 bits

2h = Response Length 48 bits

3h = Response Length 48 bits with busy after response

15-6RESERVEDR0h
5MSBSR/W0h

Multi/Single block select

This bit must be set to 1 for data transfer in case of multi-block command. For any others command, this bit is set to 0.

0h = Single block. If this bit is 0, it is not necessary to set the register MMCi.MMCHS_BLK[31:16] NBLK bits.

1h = Multi-block. When Block Count is disabled (MMCi.MMCHS_CMD[1] BCE bit is set to 0) in Multiple block transfers (MMCi.MMCHS_CMD[5] MSBS bit is set to 1), the module can perform infinite transfer.

4DDIRR/W0h

Data transfer direction

This bit defines whether either data transfer is a read or a write.

0h = Data Write (host to card)

1h = Data Read (card to host)

3-2RESERVEDR0h
1BCER/W0h

Block Count Enable (multiple block transfers only)

This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK bits). When Block Count is disabled (MMCHS_CMD[1] BCE bit is set to 0) in multiple block transfers (MMCHS_CMD[5] MSBS bits is set to 1), the module can perform infinite transfer.

0h = Block count disabled for infinite transfer

1h = Block count enabled for multiple block transfer with known number of blocks

0DER/W0h

DMA enable

This bit is used to enable DMA mode for host data access.

0h = DMA mode disable

1h = DMA mode enable

11.7.6 MMCHS_RSP10 Register (Offset = 210h) [reset = 0h]

Command Response[31:0] register

MMCHS_RSP10 is shown in Figure 11-7 and described in Table 11-10.

Return to Summary Table.

This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6.

Figure 11-7 MMCHS_RSP10 Register
313029282726252423222120191817161514131211109876543210
RSP1RSP0
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-10 MMCHS_RSP10 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP1R0h

R1/R1b (normal response) /R3/R4/R5/R5b/R6 : Command Response [39:24]

R2: Command Response [31:16]

15-0RSP0R0h

R1/R1b (normal response) /R3/R4/R5/R5b/R6 : Command Response [23:8]

R2: Command Response [15:0]

11.7.7 MMCHS_RSP32 Register (Offset = 214h) [reset = 0h]

Command Response[63:32] register

MMCHS_RSP32 is shown in Figure 11-8 and described in Table 11-11.

Return to Summary Table.

This 32-bit register holds bits positions [63:32] of command response type R2.

Figure 11-8 MMCHS_RSP32 Register
313029282726252423222120191817161514131211109876543210
RSP3RSP2
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-11 MMCHS_RSP32 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP3R0h

R2: Command Response [63:48]

15-0RSP2R0h

R2: Command Response [47:32]

11.7.8 MMCHS_RSP54 Register (Offset = 218h) [reset = 0h]

Command Response[95:64] register

MMCHS_RSP54 is shown in Figure 11-9 and described in Table 11-12.

Return to Summary Table.

This 32-bit register holds bits positions [95:64] of command response type R2.

Figure 11-9 MMCHS_RSP54 Register
313029282726252423222120191817161514131211109876543210
RSP5RSP4
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-12 MMCHS_RSP54 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP5R0h

R2: Command Response [95:80]

15-0RSP4R0h

R2: Command Response [79:64]

11.7.9 MMCHS_RSP76 Register (Offset = 21Ch) [reset = 0h]

Command Response[127:96] register

MMCHS_RSP76 is shown in Figure 11-10 and described in Table 11-13.

Return to Summary Table.

This 32-bit register holds bits positions [127:96] of command response type R2.

Figure 11-10 MMCHS_RSP76 Register
313029282726252423222120191817161514131211109876543210
RSP7RSP6
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-13 MMCHS_RSP76 Register Field Descriptions
BitFieldTypeResetDescription
31-16RSP7R0h

R1b (Auto CMD12 response): Command Response [39:24]

R2: Command Response [127:112]

15-0RSP6R0h

R1b (Auto CMD12 response): Command Response [23:8]

R2: Command Response [111:96]

11.7.10 MMCHS_DATA Register (Offset = 220h) [reset = 0h]

Data register

MMCHS_DATA is shown in Figure 11-11 and described in Table 11-14.

Return to Summary Table.

This register is the 32-bit entry point of the buffer for read or write data transfers.

The buffer size is 32 bits × 256 (1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512-byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16-bit-wise, the least significant byte (bits [7:0]) must always be written or read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register, or on the most significant byte of the last word of block transfer.

Example 1: Byte or 16-bit access

Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK

Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK

Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad

Figure 11-11 MMCHS_DATA Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-14 MMCHS_DATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data Register [31:0]

In functional mode (MMCI.MMCHS_CON[4] MODE bit set to the default value 0):

A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCi.MMCHS_PSTATE[11] BRE bit), otherwise a bad access (MMCi.MMCHS_STAT[29] BADA bit) is signaled.

A write access to this register is allowed only when the buffer write enable status is set to 1 (MMCi.MMCHS_PSTATE[10] BWE bit), otherwise a bad access (MMCi.MMCHS_STAT[29] BADA bit) is signaled and the data is not written.

11.7.11 MMCHS_PSTATE Register (Offset = 224h) [reset = 0h]

Present State register

MMCHS_PSTATE is shown in Figure 11-12 and described in Table 11-15.

Return to Summary Table.

The host can get status of the host controller from this 32-bit read-only register.

Figure 11-12 MMCHS_PSTATE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDBREBWERTAWTA
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDDLADAT1CMDI
R-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-15 MMCHS_PSTATE Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11BRER0h

Buffer read enable

This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCi.MMCHS_BLK[10:0] BLEN bits has been written in the buffer and is ready to be read.

It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCi.MMCHS_STAT[5] BRR bit).

0h = Read BLEN bytes disable

1h = Read BLEN bytes enable. Readable data exists in the buffer.

10BWER0h

Buffer Write enable

This status is used for non-DMA write transfers. It indicates if space is available for write data.

0h = There is no room left in the buffer to write BLEN bytes of data.

1h = There is enough space in the buffer to write BLEN bytes of data.

9RTAR0h

Read transfer active

This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCi.MMCHS_HCTL[17] CR bit) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request.

0h = No valid data on the mmci_dat lines

1h = Read data transfer ongoing

8WTAR0h

Write transfer active

This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCi.MMCHS_HCTL[17] CR bit) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request.

0h = No valid data on the mmci_dat lines

1h = Write data transfer ongoing

7-3RESERVEDR0h
2DLAR0h

mmci_dat line active

This status bit indicates whether one of the mmci_dat line is in use. In the case of read transactions (card to host):

This bit is set to 1 after the end bit of read command or by activating continue request MMCi.MMCHS_HCTL[17] CR bit.

This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card):

This bit is set to 1 after the end bit of write command or by activating continue request MMCi.MMCHS_HCTL[17] CR bit.

This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not "busy state" or after the busy block as a result of a stop at gap request.

0h = mmci_dat Line inactive

1h = mmci_dat Line active

1DAT1R0h

Command inhibit (mmci_dat)

This status bit is generated if either mmci_dat line is active (MMCi.MMCHS_PSTATE[2] DLA bit) or Read transfer is active (MMCi.MMCHS_PSTATE[9] RTA bit) or when a command with busy is issued.

This bit prevents the local host to issue a command.

A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCi.MMCHS_STAT[1] TC bit).

0h = Issuing of command using the mmci_dat lines is allowed

1h = Issuing of command using the mmci_dat lines is not allowed

0CMDIR0h

Command inhibit(mmci_cmd)

This status bit indicates that the mmci_cmd line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases:

After the end bit of the command response, excepted if there is a command conflict error (MMCi.MMCHS_STAT[17] CCRC bit or MMCi.MMCHS_STAT[18] CEB bit set to 1) or a Auto CMD12 is not executed (MMCi.MMCHS_AC12[0] ACNE bit).

After the end bit of the command without response (MMCi.MMCHS_CMD[17:16] RSP_TYPE bits set to "00"). In case of a command data error is detected (MMCi.MMCHS_STAT[19] CTO bit set to 1), this register is not automatically cleared.

0h = Issuing of command using mmci_cmd line is allowed

1h = Issuing of command using mmci_cmd line is not allowed

11.7.12 MMCHS_HCTL Register (Offset = 228h) [reset = 0h]

Control register

MMCHS_HCTL is shown in Figure 11-13 and described in Table 11-16.

Return to Summary Table.

This register defines the host controls to set power, wakeup, and transfer parameters.

MMCi.MMCHS_HCTL[31:24] = Wakeup control

MMCi.MMCHS_HCTL[23:16] = Block gap control

MMCi.MMCHS_HCTL[15:8] = Power control

MMCi.MMCHS_HCTL[7:0] = Host control

Figure 11-13 MMCHS_HCTL Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSDVSRESERVED
R-0hR/W-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-16 MMCHS_HCTL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11-9SDVSR/W0h

SD bus voltage select (all cards)

The host driver should set these bits to select the voltage level for the card, according to the voltage supported by the system (MMCi.MMCHS_CAPA[26] VS18 bit, MMCi.MMCHS_CAPA[25] VS30 bit, MMCi.MMCHS_CAPA[24] VS33 bit) before starting a transfer.

5h = 1.8 V (typical)

6h = 3.0 V (typical)

7h = 3.3 V (typical)

MMCHS2: This field must be set to 0x5

MMCHS3: This field must be set to 0x5

8-0RESERVEDR0h

11.7.13 MMCHS_SYSCTL Register (Offset = 22Ch) [reset = 0h]

SD System Control register

MMCHS_SYSCTL is shown in Figure 11-14 and described in Table 11-17.

Return to Summary Table.

This register defines the system controls to set software resets, clock frequency management, and data time-out.

MMCHS_SYSCTL[31:24] = Software resets

MMCHS_SYSCTL[23:16] = Timeout control

MMCHS_SYSCTL[15:0] = Clock control

Figure 11-14 MMCHS_SYSCTL Register
31302928272625242322212019181716
RESERVEDSRDSRCSRARESERVEDDTO
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
1514131211109876543210
CLKDRESERVEDCENICSICE
R/W-0hR-0hR/W-0hR-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-17 MMCHS_SYSCTL Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0h
26SRDR/W0h

Software reset for mmci_dat line

This bit is set to 1 for reset and released to 0 when completed .mmci_dat finite state machine in both clock domain are also reset. These registers are cleared by the MMCHS_SYSCTL[26] SRD bit:

MMCi.MMCHS_DATA MMCi.MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI

MMCi.MMCHS_HCTL: SBGR and CR

MMCi.MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized.

0h = Reset completed

1h = Software reset for mmci_dat line

25SRCR/W0h

Software reset for mmci_cmd line

This bit is set to 1 for reset and released to 0 when completed. mmci_cmd finite state machine in both clock domain are also reset. These are the registers cleared by the MMCi.MMCHS_SYSCTL[25] SRC bit:

MMCi.MMCHS_PSTATE: CMDI

MMCi.MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized.

0h = Reset completed

1h = Software reset for mmci_dat line

24SRAR/W0h

Software reset for all

This bit is set to 1 for reset , and released to 0 when RW 0 completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers.

0h = Reset completed

1h = Software reset for all the designs

23-20RESERVEDR0h
19-16DTOR/W0h

Data time-out counter value and busy time-out

The host driver must set this bit field based on:

  • The maximum read access time (NAC) (refer to the SD Specification Part1 Physical Layer)
  • The data read access time values (TAAC and NSAC) in the card-specific data register (CSD) of the card
  • The time-out clock base frequency (MMCi.MMCHS_CAPA[5:0] TCF bits)
If the card does not respond within the specified number of cycles, a data time-out error occurs (MMCi.MMCHS_STAT[20] DTO bit). The MMCi.MMCHS_SYSCTL[19,16] DTO bitfield is also used to check busy duration, to generate busy time-out for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write.

0h = TCF × 213

1h = TCF × 214

Eh = TCF × 227

Fh = Reserved

15-6CLKDR/W0h

Clock frequency select

These bits define the ratio between a reference RW 0x000 clock frequency (system-dependant) and the output clock frequency on the mmci_clk pin of either the memory card (MMC, SD or SDIO).

0h = Clock Ref bypass

1h = Clock Ref bypass

2h = Clock Ref / 2

3h = Clock Ref / 3

3FFh = Clock Ref / 1023

5-3RESERVEDR0h
2CENR/W0h

Clock enable

This bit controls whether the clock is provided to the card or not.

0h = The clock is not provided to the card. Clock frequency can be changed.

1h = The clock is provided to the card and can be automatically gated when MMCi.MMCHS_SYSCONFIG[0] AUTOIDLE bit is set to 1 (default value). The host driver waits to set this bit to 1 until the internal clock is stable (MMCi.MMCHS_SYSCTL[1] ICS bit).

1ICSR0h

Internal clock stable (status)

This bit indicates either the internal clock is stable or not.

0h = The internal clock is not stable

1h = The internal clock is stable after enabling the clock (MMCi.MMCHS_SYSCTL[0] ICE bit) or after changing the clock ratio (MMCi.MMCHS_SYSCTL[15:6] CLKD bits).

0ICER/W0h

Internal clock enable

This register controls the internal clock activity. In a very low-power state, the internal clock is stopped.

Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register.

0h = The internal clock is stopped (very low power state).

1h = The internal clock oscillates and can be automatically gated when MMCi.MMCHS_SYSCONFIG[0] AUTOIDLE bit is set to 1 (default value).

11.7.14 MMCHS_STAT Register (Offset = 230h) [reset = 0h]

Interrupt Status register

MMCHS_STAT is shown in Figure 11-15 and described in Table 11-18.

Return to Summary Table.

The interrupt status regroups all the status of the module internal events that can generate an interrupt.

MMCHS_STAT[31:16] = Error Interrupt Status

MMCHS_STAT[15:0] = Normal Interrupt Status

Figure 11-15 MMCHS_STAT Register
3130292827262524
RESERVEDBADACERRRESERVED
R-0hR/W-0hR/W-0hR-0h
2322212019181716
RESERVEDDEBDCRCDTORESERVEDCEBCCRCCTO
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
15141312111098
ERRIRESERVED
R-0hR-0h
76543210
RESERVEDBRRBWRRESERVEDTCCC
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-18 MMCHS_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h
29BADAR/W0h

Bad access to data space

This bit is set automatically to indicate a bad access to buffer when not allowed:

During a read access to the data register (MMCi.MMCHS_DATA) while buffer reads are not allowed (MMCi.MMCHS_PSTATE[11] BRE bit =0)

During a write access to the data register (MMCi.MMCHS_DATA) while buffer writes are not allowed (MMCi.MMCHS_PSTATE[10] BWE bit=0)

Read 0h = No interrupt

Write 0h = Status bit unchanged

Read 1h = Bad access

Write 1h = Status is cleared

28CERRR/W0h

Card error

This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5, or R5b. Only bits referenced as type E (error) in the status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCi.MMCHS_CSRE in set.

There is no card error detection for the autoCMD12 command. The host driver reads MMCi.MMCHS_RSP76 register to detect error bits in the command response.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Card error

Write 1h = Status is cleared

27-23RESERVEDR0h
22DEBR/W0h

Data End Bit error

This bit is set automatically when detecting a 0 at the end bit position of read data on mmci_dat line, or at the end position of the CRC status in write mode.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Data end bit error

Write 1h = Status is cleared

21DCRCR/W0h

Data CRC error

This bit is set automatically when there is a CRC16 error in the data phase response following a block read command, or if there is a 3-bit CRC status different of a position 010 token during a block write command.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Data CRC error

Write 1h = Status is cleared

20DTOR/W0h

Data time-out error

This bit is set automatically according to the following conditions:

  • Busy time-out for R1b, R5b response type
  • Busy time-out after write CRC status
  • Write CRC status time-out
  • Read data time-out

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Time-out

Write 1h = Status is cleared

19RESERVEDR0h
18CEBR/W0h

Command end bit error

This bit is set automatically when detecting a 0 at the end bit position of a command response.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Command end bit error

Write 1h = Status is cleared

17CCRCR/W0h

Command CRC error

This bit is set automatically when there is a CRC7 error in the command response, depending on the enable bit (MMCi.MMCHS_CMD[19] CCCE).

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Command CRC error

Write 1h = Status is cleared

16CTOR/W0h

Command time-out error

This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles, the time-out is still detected at 64 clock cycles.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Time-out

Write 1h = Status is cleared

15ERRIR0h

Error Interrupt

If any of the bits in the Error Interrupt Status register (MMCi.MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore, the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored.

0h = No interrupt

1h = Error interrupt events occurred

14-6RESERVEDR0h
5BRRR/W0h

Buffer read ready

This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by the MMCi.MMCHS_BLK[10:0] BLEN bitfield is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it.

Note: If the DMA receive-mode is enabled, this bit is never set; instead, a DMA receive request to the main DMA controller of the system is generated.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Ready to read buffer

Write 1h = Status is cleared

4BWRR/W0h

Buffer write ready

This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCi.MMCHS_BLK[10:0] BLEN. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer.

Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated.

Read 0h = No error

Write 0h = Status bit unchanged

Read 1h = Ready to write buffer

Write 1h = Status is cleared

3-2RESERVEDR0h
1TCR/W0h

Transfer completed

This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCi.MMCHS_HCTL[16] SBGR bit).

This bit is also set when exiting a command in a busy state (if the command has a busy notification capability).

In read mode: This bit is automatically set on completion of a read transfer (MMCi.MMCHS_PSTATE[9] RTA bit).

In write mode: This bit is set automatically on completion of the mmci_dat line use (MMCi.MMCHS_PSTATE[2] DLA bit).

Read 0h = No transfer complete

Write 0h = Status bit unchanged

Read 1h = Data transfer complete

Write 1h = Status is cleared

0CCR/W0h

Command complete

This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCi.MMCHS_PSTATE[0] CMDI bit)

If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command time-out error (MMCi.MMCHS_STAT[16] CTO bit) has higher priority than command complete (MMCi.MMCHS_STAT[0] CC bit).

If a response is expected but none is received, then a command time-out error is detected and signaled instead of the command complete interrupt.

Read 0h = No command complete

Write 0h = Status bit unchanged

Read 1h = Command complete

Write 1h = Status is cleared

11.7.15 MMCHS_IE Register (Offset = 234h) [reset = 0h]

Interrupt SD Enable register

MMCHS_IE is shown in Figure 11-16 and described in Table 11-19.

Return to Summary Table.

This register allows to enable or disable the module to set status bits, on an event-by-event basis.

MMCHS_IE[31:16] = Error Interrupt Status Enable

MMCHS_IE[15:0] = Normal Interrupt Status Enable

Figure 11-16 MMCHS_IE Register
3130292827262524
RESERVEDBADA_ENABLECERR_ENABLERESERVED
R-0hR/W-0hR/W-0hR-0h
2322212019181716
RESERVEDDEB_ENABLEDCRC_ENABLEDTO_ENABLERESERVEDCEB_ENABLERESERVEDCTO_ENABLE
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR-0hR/W-0h
15141312111098
NULLRESERVED
R-0hR-0h
76543210
RESERVEDBRR_ENABLEBWR_ENABLERESERVEDTC_ENABLECC_ENABLE
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-19 MMCHS_IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h
29BADA_ENABLER/W0h

Bad access to data space interrupt enable

0h = Masked

1h = Enabled

28CERR_ENABLER/W0h

Card error interrupt enable

0h = Masked

1h = Enabled

27-23RESERVEDR0h
22DEB_ENABLER/W0h

Data end bit error interrupt enable

0h = Masked

1h = Enabled

21DCRC_ENABLER/W0h

Data CRC error interrupt enable

0h = Masked

1h = Enabled

20DTO_ENABLER/W0h

Data time-out error interrupt enable

0h = The data time-out detection is deactivated. The host controller provides the clock to the card until the card sends the data or the transfer is aborted.

1h = The data time-out detection is enabled.

19RESERVEDR0h
18CEB_ENABLER/W0h

Command end bit error interrupt enable

0h = Masked

1h = Enabled

17RESERVEDR0h
16CTO_ENABLER/W0h

Command time-out error interrupt enable

0h = Masked

1h = Enabled

15NULLR0h

Fixed to 0

The host driver controls the error interrupts using the Error Interrupt Signal Enable register.

Writes to this bit are ignored.

14-6RESERVEDR0h
5BRR_ENABLER/W0h

Buffer read ready interrupt enable

0h = Masked

1h = Enabled

4BWR_ENABLER/W0h

Buffer write ready interrupt enable

0h = Masked

1h = Enabled

3-2RESERVEDR0h
1TC_ENABLER/W0h

Transfer completed interrupt enable

0h = Masked

1h = Enabled

0CC_ENABLER/W0h

Command completed interrupt enable

0h = Masked

1h = Enabled

11.7.16 MMCHS_ISE Register (Offset = 238h) [reset = 0h]

Interrupt Signal Enable register

MMCHS_ISE is shown in Figure 11-17 and described in Table 11-20.

Return to Summary Table.

This register allows to enable or disable the module internal sources of status, on an event-by-event basis.

MMCHS_ISE[31:16] = Error Interrupt Signal Enable

MMCHS_ISE[15:0] = Normal Interrupt Signal Enable

Figure 11-17 MMCHS_ISE Register
3130292827262524
RESERVEDBADA_SIGENCERR_SIGENRESERVED
R-0hR/W-0hR/W-0hR-0h
2322212019181716
RESERVEDDEB_SIGENDCRC_SIGENDTO_SIGENRESERVEDCEB_SIGENRESERVEDCTO_SIGEN
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR-0hR/W-0h
15141312111098
NULLRESERVED
R-0hR-0h
76543210
RESERVEDBRR_SIGENBWR_SIGENRESERVEDTC_SIGENCC_SIGEN
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 11-20 MMCHS_ISE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h
29BADA_SIGENR/W0h

Bad access to data space signal status enable

0h = Masked

1h = Enabled

28CERR_SIGENR/W0h

Card error interrupt signal status enable

0h = Masked

1h = Enabled

27-23RESERVEDR0h
22DEB_SIGENR/W0h

Data end bit error signal status enable

0h = Masked

1h = Enabled

21DCRC_SIGENR/W0h

Data CRC error signal status enable

0h = Masked

1h = Enabled

20DTO_SIGENR/W0h

Data time-out error signal status enable

0h = Masked

1h = Enabled

19RESERVEDR0h
18CEB_SIGENR/W0h

Command end bit error signal status enable

0h = Masked

1h = Enabled

17RESERVEDR0h
16CTO_SIGENR/W0h

Command time-out error signal status enable

0h = Masked

1h = Enabled

15NULLR0h

Fixed to 0

The host driver controls the error interrupts using the Error Interrupt Signal Enable register.

Writes to this bit are ignored.

14-6RESERVEDR0h
5BRR_SIGENR/W0h

Buffer read ready signal status enable

0h = Masked

1h = Enabled

4BWR_SIGENR/W0h

Buffer write ready signal status enable

0h = Masked

1h = Enabled

3-2RESERVEDR0h
1TC_SIGENR/W0h

Transfer completed signal status enable

0h = Masked

1h = Enabled

0CC_SIGENR/W0h

Command completed signal status enable

0h = Masked

1h = Enabled