SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

18.5 DES Registers

Table 18-7 lists the memory-mapped DES registers. All register offset addresses not listed in Table 18-7 should be considered as reserved locations and the register contents should not be modified.

The DES module comprises registers that exist at an offset relative to the DES module base address 0x4403 8000, and a small set of DES μDMA registers that exist at an offset relative to DTHE module base address 0x4403.0000.

Note:

The DES registers are limited to 32-bit data accesses; 8- and 16-bit accesses are not allowed, and can corrupt register contents.

Table 18-7 DES Register Map
OffsetAcronymRegister NameSection
830hDTHE_DES_IMDES Interrupt Mask Set RegisterSection 18.5.1
834hDTHE_DES_RISDES Interrupt Raw Interrupt Status RegisterSection 18.5.2
838hDTHE_DES_MISDES Interrupt Masked Interrupt Status RegisterSection 18.5.3
83ChDTHE_DES_ICDES Interrupt Clear Interrupt Status RegisterSection 18.5.4
1000hDES_KEY3_LDES Key 3 LSW for 192-Bit KeySection 18.5.5
1004hDES_KEY3_HDES Key 3 MSW for 192-Bit KeySection 18.5.6
1008hDES_KEY2_LDES Key 2 LSW for 128-Bit KeySection 18.5.7
100ChDES_KEY2_HDES Key 2 MSW for 128-Bit KeySection 18.5.8
1010hDES_KEY1_LDES Key 1 LSW for 64-Bit KeySection 18.5.9
1014hDES_KEY1_HDES Key 1 MSW for 64-Bit KeySection 18.5.10
1018hDES_IV_LDES Initialization VectorSection 18.5.11
101ChDES_IV_HDES Initialization VectorSection 18.5.12
1020hDES_CTRLDES ControlSection 18.5.13
1024hDES_LENGTHDES Cryptographic Data LengthSection 18.5.14
1028hDES_DATA_LDES LSW Data RWSection 18.5.15
102ChDES_DATA_HDES MSW Data RWSection 18.5.16
1034hDES_SYSCONFIGDES System ConfigurationSection 18.5.17
103ChDES_IRQSTATUSDES Interrupt StatusSection 18.5.18
1040hDES_IRQENABLEDES Interrupt EnableSection 18.5.19

18.5.1 DTHE_DES_IM Register (Offset = 830h) [reset = Dh]

DTHE_DES_IM is shown in Figure 18-8 and described in Table 18-8.

Return to Summary Table.

The interrupt mask set register lets the user control which interrupt source should interrupt the processor.

Figure 18-8 DTHE_DES_IM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDoutDinRESERVEDCin
R-0hR/W-1hR/W-1hR-0hR/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-8 DTHE_DES_IM Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DoutR/W1h

Data out: this interrupt is raised when the DMA finishes writing the last word of the process result.

2DinR/W1h

Data in: this interrupt is raised when the DMA writes the last word of input data to the internal FIFO of the engine.

1RESERVEDR0h
0CinR/W1h

Context in: this interrupt is raised when the DMA completes context write to the internal register.

18.5.2 DTHE_DES_RIS Register (Offset = 834h) [reset = 0h]

DTHE_DES_RIS is shown in Figure 18-9 and described in Table 18-9.

Return to Summary Table.

Raw Interrupt Status register

Figure 18-9 DTHE_DES_RIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDoutDinRESERVEDCin
R-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-9 DTHE_DES_RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DoutR0h

Output Data movement is done.

2DinR0h

Input Data movement is done.

1RESERVEDR0h
0CinR0h

Context input is done.

18.5.3 DTHE_DES_MIS Register (Offset = 838h) [reset = 0h]

DTHE_DES_MIS is shown in Figure 18-10 and described in Table 18-10.

Return to Summary Table.

Masked Interrupt Status register

Figure 18-10 DTHE_DES_MIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDoutDinRESERVEDCin
R-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-10 DTHE_DES_MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DoutR0h

Output Data movement is done.

2DinR0h

Input Data movement is done.

1RESERVEDR0h
0CinR0h

Context input is done.

18.5.4 DTHE_DES_IC Register (Offset = 83Ch) [reset = 0h]

DTHE_DES_IC is shown in Figure 18-11 and described in Table 18-11.

Return to Summary Table.

Interrupt Acknowledge register. Writing 1 to these bits clears the status flag in the IRIS and IMIS registers. Always reads zero.

Figure 18-11 DTHE_DES_IC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDoutDinRESERVEDCin
R-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-11 DTHE_DES_IC Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3DoutR0h

Clear “output data movement done” flag.

2DinR0h

Clear “input data movement done” flag.

1RESERVEDR0h
0CinR0h

Clear “context input done” flag.

18.5.5 DES_KEY3_L Register (Offset = 1000h) [reset = 0h]

DES_KEY3_L is shown in Figure 18-12 and described in Table 18-12.

Return to Summary Table.

KEY3 (LSW) for 192-bit key.

Figure 18-12 DES_KEY3_L Register
313029282726252423222120191817161514131211109876543210
KEY3_L
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-12 DES_KEY3_L Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY3_LR/W0h

Data for key3

18.5.6 DES_KEY3_H Register (Offset = 1004h) [reset = 0h]

DES_KEY3_H is shown in Figure 18-13 and described in Table 18-13.

Return to Summary Table.

KEY3 (MSW) for 192-bit key.

Figure 18-13 DES_KEY3_H Register
313029282726252423222120191817161514131211109876543210
KEY3_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-13 DES_KEY3_H Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY3_HR/W0h

Data for key3

18.5.7 DES_KEY2_L Register (Offset = 1008h) [reset = 0h]

DES_KEY2_L is shown in Figure 18-14 and described in Table 18-14.

Return to Summary Table.

KEY2 (LSW) for 192-bit key.

Figure 18-14 DES_KEY2_L Register
313029282726252423222120191817161514131211109876543210
KEY2_L
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-14 DES_KEY2_L Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY2_LR/W0h

Data for key2

18.5.8 DES_KEY2_H Register (Offset = 100Ch) [reset = 0h]

DES_KEY2_H is shown in Figure 18-15 and described in Table 18-15.

Return to Summary Table.

KEY2 (MSW) for 192-bit key.

Figure 18-15 DES_KEY2_H Register
313029282726252423222120191817161514131211109876543210
KEY2_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-15 DES_KEY2_H Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY2_HR/W0h

Data for key2

18.5.9 DES_KEY1_L Register (Offset = 1010h) [reset = 0h]

DES_KEY1_L is shown in Figure 18-16 and described in Table 18-16.

Return to Summary Table.

KEY1 (LSW) for 192-bit key.

Figure 18-16 DES_KEY1_L Register
313029282726252423222120191817161514131211109876543210
KEY1_L
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-16 DES_KEY1_L Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY1_LR/W0h

Data for key1

18.5.10 DES_KEY1_H Register (Offset = 1014h) [reset = 0h]

DES_KEY1_H is shown in Figure 18-17 and described in Table 18-17.

Return to Summary Table.

KEY1 (MSW) for 192-bit key.

Figure 18-17 DES_KEY1_H Register
313029282726252423222120191817161514131211109876543210
KEY1_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-17 DES_KEY1_H Register Field Descriptions
BitFieldTypeResetDescription
31-0KEY1_HR/W0h

Data for key1

18.5.11 DES_IV_L Register (Offset = 1018h) [reset = 0h]

DES_IV_L is shown in Figure 18-18 and described in Table 18-18.

Return to Summary Table.

Initialization vector LSW

Figure 18-18 DES_IV_L Register
313029282726252423222120191817161514131211109876543210
IV_L
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-18 DES_IV_L Register Field Descriptions
BitFieldTypeResetDescription
31-0IV_LR/W0h

Initialization vector for CBC, CFB modes.

18.5.12 DES_IV_H Register (Offset = 101Ch) [reset = 0h]

DES_IV_H is shown in Figure 18-19 and described in Table 18-19.

Return to Summary Table.

Initialization vector MSW

Figure 18-19 DES_IV_H Register
313029282726252423222120191817161514131211109876543210
IV_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-19 DES_IV_H Register Field Descriptions
BitFieldTypeResetDescription
31-0IV_HR/W0h

Initialization vector for CBC, CFB modes.

18.5.13 DES_CTRL Register (Offset = 1020h) [reset = 80000000h]

DES_CTRL is shown in Figure 18-20 and described in Table 18-20.

Return to Summary Table.

Figure 18-20 DES_CTRL Register
3130292827262524
CONTEXTRESERVED
RO-1hRO-0h
2322212019181716
RESERVED
RO-0h
15141312111098
RESERVED
RO-0h
76543210
RESERVEDMODETDESDIRECTIONINPUT_READYOUTPUT_READY
RO-0hR/W-0hR/W-0hR/W-0hRO-0hRO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-20 DES_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31CONTEXTRO1h

If 1, this read-only status bit indicates that the context data registers can be overwritten and the host is permitted to write the next context.

30-6RESERVEDRO0h
5-4MODER/W0h

Select CBC, ECB or CFB mode.

0h = ECB mode

1h = CBC mode

2h = CFB mode

3h = Reserved

3TDESR/W0h

Select DES or triple DES encryption or decryption.

0h = DES mode

1h = TDES mode

2DIRECTIONR/W0h

Select encryption or decryption.

0h = Decryption is selected

1h = Encryption is selected

1INPUT_READYRO0h

When 1, ready to encrypt or decrypt data.

0OUTPUT_READYRO0h

When 1, data decrypted or encrypted ready.

18.5.14 DES_LENGTH Register (Offset = 1024h) [reset = 0h]

DES_LENGTH is shown in Figure 18-21 and described in Table 18-21.

Return to Summary Table.

Figure 18-21 DES_LENGTH Register
313029282726252423222120191817161514131211109876543210
LENGTH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-21 DES_LENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0LENGTHR/W0h

Indicates the cryptographic data length in bytes for all modes. Once processing is started with this context, this length decrements to zero. Data lengths up to (232 – 1) bytes are allowed. A write to this register triggers the engine to start using this context. For a host read operation, these registers return all zeroes.

18.5.15 DES_DATA_L Register (Offset = 1028h) [reset = 0h]

DES_DATA_L is shown in Figure 18-22 and described in Table 18-22.

Return to Summary Table.

Data register (LSW) to read/write encrypted or decrypted data.

Figure 18-22 DES_DATA_L Register
313029282726252423222120191817161514131211109876543210
DATA_L
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-22 DES_DATA_L Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA_LR/W0h

Data for encryption or decryption

18.5.16 DES_DATA_H Register (Offset = 102Ch) [reset = 0h]

DES_DATA_H is shown in Figure 18-23 and described in Table 18-23.

Return to Summary Table.

Data register (MSW) to read/write encrypted or decrypted data.

Figure 18-23 DES_DATA_H Register
313029282726252423222120191817161514131211109876543210
DATA_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-23 DES_DATA_H Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA_HR/W0h

Data for encryption or decryption

18.5.17 DES_SYSCONFIG Register (Offset = 1034h) [reset = 0h]

DES_SYSCONFIG is shown in Figure 18-24 and described in Table 18-24.

Return to Summary Table.

Figure 18-24 DES_SYSCONFIG Register
3130292827262524
RESERVED
RO-0h
2322212019181716
RESERVED
RO-0h
15141312111098
RESERVED
RO-0h
76543210
DMA_REQ_CONTEXT_IN_ENDMA_REQ_DATA_OUT_ENDMA_REQ_DATA_IN_ENRESERVED
R/W-0hR/W-0hR/W-0hRO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-24 DES_SYSCONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRO0h
7DMA_REQ_CONTEXT_IN_ENR/W0h

If set to 1, the DMA context request is enabled.

0h = DMA disabled

1h = DMA enabled

6DMA_REQ_DATA_OUT_ENR/W0h

If set to 1, the DMA output request is enabled.

0h = DMA disabled

1h = DMA enabled

5DMA_REQ_DATA_IN_ENR/W0h

If set to 1, the DMA input request is enabled.

0h = DMA disabled

1h = DMA enabled

4-0RESERVEDRO0h

18.5.18 DES_IRQSTATUS Register (Offset = 103Ch) [reset = 0h]

DES_IRQSTATUS is shown in Figure 18-25 and described in Table 18-25.

Return to Summary Table.

This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is asserted.

Figure 18-25 DES_IRQSTATUS Register
3130292827262524
RESERVED
RO-0h
2322212019181716
RESERVED
RO-0h
15141312111098
RESERVED
RO-0h
76543210
RESERVEDDATA_OUTDATA_INCONTEX_IN
RO-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-25 DES_IRQSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRO0h
2DATA_OUTR/W0h

This bit indicates data output interrupt is active and triggers the interrupt output.

1DATA_INR/W0h

This bit indicates data input interrupt is active and triggers the interrupt output.

0CONTEX_INR/W0h

This bit indicates context interrupt is active and triggers the interrupt output.

18.5.19 DES_IRQENABLE Register (Offset = 1040h) [reset = 0h]

DES_IRQENABLE is shown in Figure 18-26 and described in Table 18-26.

Return to Summary Table.

This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1.

Figure 18-26 DES_IRQENABLE Register
3130292827262524
RESERVED
RO-0h
2322212019181716
RESERVED
RO-0h
15141312111098
RESERVED
RO-0h
76543210
RESERVEDM_DATA_OUTM_DATA_INM_CONTEX_IN
RO-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-26 DES_IRQENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRO0h
2M_DATA_OUTR/W0h

If this bit is set to 1, the data output interrupt is enabled.

1M_DATA_INR/W0h

If this bit is set to 1, the data input interrupt is enabled.

0M_CONTEX_INR/W0h

If this bit is set to 1, the context interrupt is enabled.