TIDT328 april   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Considerations
    3. 1.3 Dimensions
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Load Regulation
    3. 2.3 Thermal Images
      1. 2.3.1 Unmodulated 60 VDC - Output
      2. 2.3.2 60 VAC - Output Modulated With 120-Hz Sinus (0 V – 5 V)
      3. 2.3.3 Conclusion
    4. 2.4 Bode Plot at Maximum Duty Cycle
  7. 3Waveforms
    1. 3.1 Switching
      1. 3.1.1 Transistor Q1 Operating in Deep DCM
        1. 3.1.1.1 Drain to Source
        2. 3.1.1.2 Gate to Source
      2. 3.1.2 Diode D3 (Referenced to VOUT)
    2. 3.2 Output Voltage Ripple
    3. 3.3 Input Voltage Ripple
    4. 3.4 Start-Up Sequence
    5. 3.5 Shutdown Sequence
  8.   A Modulating the Output Voltage
    1.     A.1 Revision B
      1.      A.1.1 Bode Plot
      2.      A.1.2 Simulation
      3.      A.1.3 Measured Waveforms
        1.       A.1.3.1 Sinus 40 Hz
        2.       A.1.3.2 Sinus 100 Hz
        3.       A.1.3.3 Sawtooth 1
        4.       A.1.3.4 Sawtooth 2
        5.       A.1.3.5 Pure Triangle
        6.       A.1.3.6 Conclusion
    2.     A.2 Revision C
      1.      A.2.1 Bode Plot
      2.      A.2.2 Measured Waveforms
        1.       A.2.2.1 Sinus 120 Hz
        2.       A.2.2.2 Sawtooth 1
        3.       A.2.2.3 Sawtooth 2
        4.       A.2.2.4 Pure Triangle
      3.      A.2.3 Analysis Capacitor 1 µF, 100 V, X7R, 1206
        1.       A.2.3.1 DC-Bias
        2.       A.2.3.2 Resistance (ESR)
        3.       A.2.3.3 Reactance
        4.       A.2.3.4 Impedance

A.1.3.6 Conclusion

The reason for the nonlinearity in before minimum of the sinusoidal waveform at a certain point is that the small load current is not able to discharge the output capacitor fast enough; the output voltage cannot follow the modulation voltage anymore.

To enable high frequency modulation or more negative slope needs synchronous rectification in FPWM mode to discharge the output capacitor towards the power stage.

The output capacitance needs to be decreased, and the loop needs to be adjusted to the bigger load pole:

  • Reduce gain to keep FCO around 10 kHz
  • Set compensation zero to 2 × load pole
  • Adjust compensation pole to keep pole frequency around 100 kHz. For achieving higher linearity at Fmod, the output capacitance must be further reduced.

A rough linear estimation can be obtained with the following equations.

Equation 1. Energy at output capacitor: Q = C × V = I × t

Use Equation 2 to calculate the current needed to reduce the output voltage at an output capacitance of 5 µF by –10 V within 1 ms.

Equation 2. Time discrete: I = C × d u d t = 5   µ F × 10   V 1   m s = 50   m A

Equation 3 shows the current across a load resistance of 200 Ω at a low output voltage of 10 V.

Equation 3. Load current: I = 10   V / 200   Ω = 50   m A

Means by decreasing the sinusoidal output voltage below 10 V, the output is no longer able to follow the modulation, the sinusoidal voltage moves towards an e-function, resistive discharging of the output capacitor 5 µF. The non-synchronous rectification and the simple Schottky diode allows no current to go in the opposite direction to the power stage – the resolution steps are shown in the following list:

  • Minimize output capacitance
  • Synchronous rectification, no diode emulation
  • Digital pre-distortion of the modulating signal, but negative slope is always limited