TIDUF28 November   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 LMG3422R030
      2. 2.2.2 ISO7741
      3. 2.2.3 AMC1306M05
      4. 2.2.4 AMC1035
      5. 2.2.5 TPSM560R6H
      6. 2.2.6 TPSM82903
  9. 3System Design Theory
    1. 3.1 Power Switches
      1. 3.1.1 GaN-FET Selection Criterion
      2. 3.1.2 HVBUS Decoupling and 12-V Bootstrap Supply
      3. 3.1.3 GaN_FET Turn-on Slew Rate Configuration
      4. 3.1.4 PWM Input Filter and Dead-Time Calculation
      5. 3.1.5 Signal Level Shifting
      6. 3.1.6 LMG3422R030 Fault Reporting
      7. 3.1.7 LMG3422R030 Temperature Monitoring
    2. 3.2 Phase Current Sensing
      1. 3.2.1 Shunt
      2. 3.2.2 AMC1306M05 Analog Input-Filter
      3. 3.2.3 AMC1306M05 Digital Interface
      4. 3.2.4 AMC1306M05 Supply
    3. 3.3 DC-Link (HV_BUS) Voltage Sensing
    4. 3.4 Phase Voltage Sensing
    5. 3.5 Control Supply
    6. 3.6 MCU Interface
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 PCB
      2. 4.1.2 MCU Interface
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
      1. 4.3.1 Precautions
      2. 4.3.2 Test Procedure
    4. 4.4 Test Results
      1. 4.4.1 24-V Input Control Supply
      2. 4.4.2 Propagation Delay PWM to Phase Voltage Switch Node
      3. 4.4.3 Switch Node Transient at 320-VDC Bus Voltage
      4. 4.4.4 Phase Voltage Linearity and Distortion at 320 VDC and 16-kHz PWM
      5. 4.4.5 Inverter Efficiency and Thermal Characteristic
        1. 4.4.5.1 Efficiency Measurements
        2. 4.4.5.2 Thermal Analysis and SOA Without Heat Sink at 320 VDC and 16-kHz PWM
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 Layout Prints
      4. 5.1.4 Altium Project
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

3.1.2 HVBUS Decoupling and 12-V Bootstrap Supply

Although the LMG3422R030 GaN-FETs are rated for 600-V, this design is rated for 400 VDC (MAX). The PCB clearance between traces or polygons on each copper layer with voltages higher than 60 VDC or 25 VAC between each other is minimum 0.8 mm for inner layers and 1.6 mm for the top and bottom layers.

The design uses a multichannel schematic with the same components for each of the three half-bridges. To distinguish between the phase _U, _V, or _W are appended to the component designators. In the following description the phase designator is not shown, for example instead of R20_U, R20_V, and R20_W, just R20 is used.

Figure 3-2 shows the schematic of a half-bridge phase V with two 600-V rated LMG3422R030 devices. Each half-bridge has four parallel decoupling capacitors across HVBUS and GND, 2-times 10 nF and 2-times 100 nF, rated 1 kV.

A 12-VDC non-isolated rail supplies the three bottom-side LMG3422R030 devices. A bootstrap configuration using a high-voltage diode D1, a 3.3-Ω current limit resistor R6, and a 10-uF bulk capacitor C1 provide a floating 12-V supply for the each of the three top-side LMG34022R030 devices. A 16-V Zener diode in parallel to the C1 bulk capacitor makes sure the supply voltage of the LMG3422R030 remains below the VDD maximum recommended voltage of 18 V. This is required since during third quadrant operation the switch node voltage is lower than GND and the bootstrap capacitor can be charged up to sum of the 12-V supply rail and the third quadrant source-to-drain voltage VSD, which is typically 5 V at 20-A source current. Due to the large C1 bulk capacitor of 10-uF and the 3.3-Ω current limit resistor R6, the bottom-side GaN-FETs need to be turned on long enough after power up to make sure the C1 bulk capacitor is charged close to 12 V, before the top-side GaN-FETs are turned on.

For the LMG3422R030 integrated buck-boost converter, a 4.7-μH inductor is placed from the LMG3422R030 BBSW pin to the switch node floating ground (top-side GaN-FET) and GND (bottom side GaN-FET), respectively. A 2.2-µF capacitor bypasses the internal buck-boost converter negative output (VNEG), which is used to turn off the depletion mode GaN-FET.