SLUSAQ9B December   2011  – December 2015 UC1875-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CLKSYNC
      2. 8.3.2  E/AOUT
      3. 8.3.3  CS+
      4. 8.3.4  FREQSET
      5. 8.3.5  DELSETA-B, DELSETC-D
      6. 8.3.6  EA-
      7. 8.3.7  EA+
      8. 8.3.8  GND
      9. 8.3.9  OUTA - OUTD
      10. 8.3.10 PWRGND
      11. 8.3.11 RAMP
      12. 8.3.12 SLOPE
      13. 8.3.13 SOFTSTART
      14. 8.3.14 VC
      15. 8.3.15 VIN
      16. 8.3.16 VREF
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Lockout Section
      2. 9.1.2 Synchronizing the Oscillator
      3. 9.1.3 Syncing to External TTL/CMOS
      4. 9.1.4 Delay Blocks and Output Stages
      5. 9.1.5 Output Switch Orientation
      6. 9.1.6 Fault/Soft Start
      7. 9.1.7 Slope/Ramp Pins
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Phase-Shifted Fundamentals
        2. 9.2.2.2  Circuit Schematic and Description
        3. 9.2.2.3  Initial Conditions (Time: t = t(0))
        4. 9.2.2.4  Right Leg Resonant Transition Interval (Time: t(0) < t < t(1))
        5. 9.2.2.5  Clamped Freewheeling Interval (Time: t(1) < t < t(2))
        6. 9.2.2.6  Left Leg Transition Interval (Time: t(2) < t < t(3))
        7. 9.2.2.7  Power Transfer Interval (Time: t(3) < t < t(4))
        8. 9.2.2.8  Switch Turn Off (Time: t(4))
        9. 9.2.2.9  Resonant Tank Considerations
        10. 9.2.2.10 Resonant Circuit Limitations
        11. 9.2.2.11 Stored Inductive Energy
        12. 9.2.2.12 Resonant Circuit Summary
        13. 9.2.2.13 Stored Energy Requirements
        14. 9.2.2.14 Minimum Primary Current
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground (GND)
      2. 11.1.2 Bias Supply (VCC)
      3. 11.1.3 Feedback Traces
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
      6. 11.1.6 Current Transformer
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • QML-V Qualified, SMD 5962-94555
  • Rad-Tolerant: 50 kRad (Si) TID (1)
  • Zero to 100% Duty Cycle Control
  • Programmable Output Turn-On Delay
  • Compatible with Voltage or Current Mode Topologies
  • Practical Operation at Switching Frequencies to
    1 MHz
  • Four 2-A Totem Pole Outputs
  • 10-MHz Error Amplifier
  • Undervoltage Lockout (UVLO)
  • Low Startup Current – 150 µA
  • Outputs Active Low During UVLO
  • Soft-Start Control
  • Latched Overcurrent Comparator With Full Cycle Restart
  • Trimmed Reference
(1)
(1)Radiation tolerance is a typical value based upon initial device qualification with a dose rate = 10 mrad/sec and applies to the 5962-9455502 devices. Radiation lot acceptance testing is available – contact factory for details.

2 Applications

    Power FPGAs

3 Description

The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current mode operation, with a separate overcurrent shutdown for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D).

With the oscillator capable of operation at frequencies in excess of 2 MHz, overall switching frequencies to
1 MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
UC1875-SP LCCC (28) 11.43 mm × 11.43 mm
CDIP (20) 24.20 mm × 6.92 mm
CFP (24) 14.36 mm × 9.09 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

UC1875-SP FBD_lusaq9.png