JAJSGZ1C
September 2015 – February 2019
TPS65094
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Device Options
3.1
OTP Comparison
4
Pin Configuration and Functions
RSK Package 64-Pin VQFN With Thermal Pad Top View
Pin Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics: Total Current Consumption
5.6
Electrical Characteristics: Reference and Monitoring System
5.7
Electrical Characteristics: Buck Controllers
5.8
Electrical Characteristics: Synchronous Buck Converters
5.9
Electrical Characteristics: LDOs
5.10
Electrical Characteristics: Load Switches
5.11
Digital Signals: I2C Interface
5.12
Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
5.13
Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
5.14
Timing Requirements
5.15
Switching Characteristics
5.16
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power Good (PGOOD)
6.3.2
Register Reset Conditions
6.3.3
SMPS Voltage Regulators
6.3.3.1
Controller Overview
6.3.3.2
Converter Overview
6.3.3.3
DVS
6.3.3.4
Current Limit
6.3.4
LDOs and Load Switches
6.3.4.1
VTT LDO
6.3.4.2
LDOA1–LDOA3
6.3.4.3
Load Switches
6.3.5
Power Sequencing and VR Control
6.3.5.1
Cold Boot
6.3.5.2
Cold OFF
6.3.5.3
Connected Standby Entry and Exit
6.3.5.4
S0 to S3 Entry and Exit
6.3.5.5
S0 to S4/5 Entry and Exit
6.3.5.6
Emergency Shutdown
6.4
Device Functional Modes
6.4.1
Off Mode
6.4.2
Standby Mode
6.4.3
Active Mode
6.5
Programming
6.5.1
I2C Interface
6.5.1.1
F/S-Mode Protocol
6.6
Register Maps
6.6.1
VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
Table 6-12
VENDORID Register Field Descriptions
6.6.2
DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
Table 6-13
DEVICEID Register Field Descriptions
6.6.3
IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
Table 6-14
IRQ Register Field Descriptions
6.6.4
IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
Table 6-15
IRQ_MASK Register Field Descriptions
6.6.5
PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
Table 6-16
PMICSTAT Register Field Descriptions
6.6.6
OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
Table 6-17
OFFONSRC Register Field Descriptions
6.6.7
BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
Table 6-18
BUCK1CTRL Register Field Descriptions
6.6.8
BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
Table 6-19
BUCK2CTRL Register Field Descriptions
6.6.9
BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
Table 6-20
BUCK3CTRL Register Field Descriptions
6.6.10
BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = 0011 1101]
Table 6-21
BUCK4CTRL Register Field Descriptions
6.6.11
BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = 0011 1101]
Table 6-22
BUCK5CTRL Register Field Descriptions
6.6.12
BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
Table 6-23
BUCK6CTRL Register Field Descriptions
6.6.13
DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
Table 6-24
DISCHCNT1 Register Field Descriptions
6.6.14
DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
Table 6-25
DISCHCNT2 Register Field Descriptions
6.6.15
DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
Table 6-26
DISCHCNT3 Register Field Descriptions
6.6.16
POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
Table 6-27
POK_DELAY Register Field Descriptions
6.6.17
FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
Table 6-28
FORCESHUTDN Register Field Descriptions
6.6.18
BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
Table 6-29
BUCK4VID Register Field Descriptions
6.6.19
BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
Table 6-30
BUCK5VID Register Field Descriptions
6.6.20
BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
Table 6-31
BUCK6VID Register Field Descriptions
6.6.21
LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
Table 6-32
LDOA2VID Register Field Descriptions
6.6.22
LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
Table 6-33
LDOA3VID Register Field Descriptions
6.6.23
VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = 0000 0111]
Table 6-34
VR_CTRL1 Register Field Descriptions
6.6.24
VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
Table 6-35
VR_CTRL2 Register Field Descriptions
6.6.25
VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = 0111 0000]
Table 6-36
VR_CTRL3 Register Field Descriptions
6.6.26
GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
Table 6-37
GPO_CTRL Register Field Descriptions
6.6.27
PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
Table 6-38
PWR_FAULT_MASK1 Register Field Descriptions
6.6.28
PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
Table 6-39
PWR_FAULT_MASK2 Register Field Descriptions
6.6.29
DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
Table 6-40
DISCHNT4 Register Field Descriptions
6.6.30
LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
Table 6-41
LDOA1CTRL Register Field Descriptions
6.6.31
PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
Table 6-42
PG_STATUS1 Register Field Descriptions
6.6.32
PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
Table 6-43
PG_STATUS2 Register Field Descriptions
6.6.32.1
PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
Table 6-44
PWR_FAULT_STATUS1 Register Field Descriptions
6.6.32.2
PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
Table 6-45
PWR_FAULT_STATUS2 Register Field Descriptions
6.6.33
TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
Table 6-46
TEMPHOT Register Field Descriptions
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Controller Design Procedure
7.2.2.1.1
Selecting the Output Capacitors
7.2.2.1.2
Selecting the Inductor
7.2.2.1.3
Selecting the FETs
7.2.2.1.4
Bootstrap Capacitor
7.2.2.1.5
Selecting the Input Capacitors
7.2.2.1.5.1
Setting the Current Limit
7.2.2.2
Converter Design Procedure
7.2.2.2.1
Selecting the Inductor
7.2.2.2.2
Selecting the Output Capacitors
7.2.2.2.3
Selecting the Input Capacitors
7.2.2.3
LDO Design Procedure
7.2.3
Application Curves
7.3
Specific Application for TPS650944
7.4
Do's and Don'ts
8
Power Supply Recommendations
9
Layout
9.1
Layout Guidelines
9.2
Layout Example
10
デバイスおよびドキュメントのサポート
10.1
デバイス・サポート
10.1.1
Third-Party Products Disclaimer
10.1.2
開発サポート
10.2
ドキュメントのサポート
10.2.1
関連資料
10.3
ドキュメントの更新通知を受け取る方法
10.4
Community Resources
10.5
商標
10.6
静電気放電に関する注意事項
10.7
Glossary
11
メカニカル、パッケージ、および注文情報
11.1
Package Option Addendum
11.1.1
Packaging Information
11.1.2
Tape and Reel Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSK|64
MPQF192B
サーマルパッド・メカニカル・データ
RSK|64
QFND521
発注情報
jajsgz1c_oa
jajsgz1c_pm
1
デバイスの概要