DLPS284 December   2025 DLP3940S-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12.     18
    13. 5.10 Micromirror Array Physical Characteristics
    14.     20
    15. 5.11 Micromirror Array Optical Characteristics
    16. 5.12 Window Characteristics
    17. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 Power Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
      5. 7.2.5 Design Requirements
      6. 7.2.6 Detailed Design Procedure
    3. 7.3 Temperature Sensing
      1. 7.3.1 Temperature Sensing Diode
        1. 7.3.1.1 Temperature Sense Diode Theory
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
    3. 8.3 DMD Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER (6) TEST CONDITIONS (2) MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD(3)(4) Typical 140 mA
IDDI Supply current: VDDI(3)(4) Typical 45 mA
IOFFSET Supply current: VOFFSET(5) Typical 6 mA
IBIAS Supply current: VBIAS(5) Typical 0.6 mA
IRESET Supply current: VRESET Typical 1.8 mA
POWER
PDD Supply power dissipation: VDD(3)(4) Typical 252 mW
PDDI Supply power dissipation: VDDI(3)(4) Typical 81 mW
POFFSET Supply power dissipation: VOFFSET(5) Typical 60 mW
PBIAS Supply power dissipation: VBIAS(5) Typical 1.08 mW
PRESET Supply power dissipation: VRESET Typical 25.2 mW
PTOTAL Supply power dissipation Total Typical 419.28 mW
LPSDR INPUT
IIL Low level input current VDD = 1.95V, VI = 0V -100 nA
IIH High level input current VDD = 1.95V, VI = 1.95V 135 uA
LPSDR OUTPUT
VOH DC output high voltage (7)(8)(9) IOH = -2 mA 0.8 x VDD V
VOL DC output low voltage (7)(8)(9) IOL = 2 mA 0.2 x VDD V
CAPACITANCE
CIN Input capacitance LVCMOS F = 1 MHz 10 pF
CIN Input capacitance SubLVDS F = 1 MHz 20 pF
COUT Output capacitance F = 1 MHz 10 pF
CTEMP Temperature sense diode capacitance F = 1 MHz 20 pF
(1) Device electrical characteristics are over Section 5.4 unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDI – VDD | must be less than the specified limit.
(4) Supply power dissipation based on non–compressed commands and data.
(5) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than the specified limit.
(6) All power supply connections are required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(8) The low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209-2F, Low-Power Double Data Rate (LPDDR) JESD209-2F.
(9) LPSDR output specification is for pins LS_RDATA_A, LS_RDATA_B, LS_RDATA_C, and LS_RDATA_D.