DLPS284 December   2025 DLP3940S-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12.     18
    13. 5.10 Micromirror Array Physical Characteristics
    14.     20
    15. 5.11 Micromirror Array Optical Characteristics
    16. 5.12 Window Characteristics
    17. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 Power Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
      5. 7.2.5 Design Requirements
      6. 7.2.6 Detailed Design Procedure
    3. 7.3 Temperature Sensing
      1. 7.3.1 Temperature Sensing Diode
        1. 7.3.1.1 Temperature Sense Diode Theory
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
    3. 8.3 DMD Power Supply Sequencing Requirements
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.2.1 Application Overview

Figure 7-1 shows the system block diagram for a DLP module. The system uses the DLPC231S-Q1, TPS99002S-Q1, and the DLP3940S-Q1 automotive DMD. The combination of the DLPC231S-Q1 and TPS99002S-Q1 removes the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination control of LED sources, power sequencing functions, and system management functions. Additionally, the chipset supports numerous system diagnostic and built-in self-test (BIST) features.

The DLPC231S-Q1 is a controller for the DMD and the light sources in the DLP module. It receives input video from the host and synchronizes DMD and light source timing to achieve the desired video. The DLPC231S-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with light source timing to create a video with grayscale shading and multiple colors, if applicable.

The DLPC231S-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input video data. Host commands can be sent using either the I2C bus or the SPI bus. The bus that is not being used for host commands can be used as a read-only bus for diagnostic purposes. The input video can be sent over an OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits or 16-bits of data for single light source or dual light source systems depending on the system design. The SPI flash memory provides the embedded software for the DLPC231S-Q1’s ARM core, any calibration data, and default settings. The TPS99002S-Q1 provides diagnostic and monitoring information to the DLPC231S-Q1 using a SPI bus and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The TMP411A-Q1 uses an I2C interface to provide the DMD array temperature to the DLPC231S-Q1.

The outputs of the DLPC231S-Q1 are configuration and monitoring commands to the TPS99002S-Q1, timing controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics information to the host processor. The DLPC231S-Q1 communicates with the TPS99002S-Q1 over an SPI bus. It uses this to configure the TPS99002S-Q1 and to read monitoring and diagnostics information from the TPS99002S-Q1. The DLPC231S-Q1 sends drive-enable signals to the LED or laser driver, and synchronizes this with the DMD mirror timing. The control signals to the DMD are sent using a SubLVDS interface.

The TPS99002S-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and diagnostics information for the DLP system. The power sequencing and monitoring blocks of the TPS99002S-Q1 properly power up the DMD and provide accurate DMD voltage rails (–14V, 10V, and 18V), and then monitor the system’s power rails during operation. The integration of these functions into one IC significantly reduces design time and complexity. The TPS99002S-Q1 also has several output signals that can be used to control a variety of LED or laser driver topologies. The TPS99002S-Q1 has several general-purpose ADCs that designers can use for system-level monitoring, such as over-brightness detection.

The TPS99002S-Q1 receives inputs from the DLPC231S-Q1, the power rails it monitors, the host processor, and potentially several other ADC ports. The DLPC231S-Q1 sends configuration and control commands to the TPS99002S-Q1 over an SPI bus and several other control signals. The DLPC231S-Q1’s clocks are also monitored by the watchdogs in the TPS99002S-Q1 to detect any errors. The power rails are monitored by the TPS99002S-Q1 to detect power failures or glitches and request a proper power down of the DMD in case of an error. The host processor can read diagnostics information from the TPS99002S-Q1 using a dedicated SPI bus, which enables independent monitoring. Additionally, the host can request the image to be turned on or off using a PROJ_ON signal. Lastly, the TPS99002S-Q1 has several general-purpose ADCs that can be used to implement system-level monitoring functions.

The outputs of the TPS99002S-Q1 are diagnostic information and error alerts to the DLPC231S-Q1, and control signals to the LED or laser driver. The TPS99002S-Q1 can output diagnostic information to the host and the DLPC231S-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the DLPC231S-Q1 that trigger power down or reset sequences. It also has output signals that can be used to implement various LED or laser driver topologies.

The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as input (video data) and produces a mechanical output (mirror position). The electrical interface to the DMD is a SubLVDS interface with the DLPC231S-Q1. The mechanical output is the state of more than 2.1 million mirrors in the DMD array that can be tilted ±14.5°. In a projection system, the mirrors are used as pixels to display an image.