DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

4.3.3.8 Four Channels 12 Lanes Top Level RTL Wrapper

Figure 4-17 showing aurora_apps_tx_x12ln.v has four instantiation of module aurora_apps_tx_x3ln_channel_wrapper.v to form the four Aurora TX channels entity.

Tx_out_clk from channel 0 feeds into aurora_apps_tx_x3ln_clock_module.v to generate the clk_user which drive the Apps FPGA and Aurora user logics interface. Refer to the Xilinx app note Chapter 2 Table 2-7: Aurora 64B/66B Core Clock Ports and Chapter 3 Figure 3-1 Aurora 64B/66B Clocking Architecture for information regarding tx_out_clk and clk_user.

Note: For link speed of 10Gbps with 64B/66B interface, clk_user frequency = 10GHz / 64 = 156.25MHz.

Reset logics generate reset signals reset_pb and pma_init to the four Aurora TX channels. Refer to the Xilinx app note Chapter 3, Figure 3-5 Aurora 64B/66B Simplex Normal Operation Reset Sequence for specification of generating reset_pb and pma_init.

GUID-20240223-SS0I-S4XC-79VC-GFGLB50SLMZR-low.png Figure 4-17 Aurora_apps_tx_x12ln.v RTL Block Diagram
Table 4-1 Signal Port List for RTL aurora_apps_tx_x12ln.v
Name Direction Clock Domain Description
clk_init Input clk_init 100MHz free running clock for generate reset signals to Aurora cores.
arstz_ui Input async Active low reset input. Input low trigger reset operation to Aurora cores.
dlpc964_initdone_ui Input async DLPC964 Controller INIT_DONE status signal. Low keeps Aurora cores in reset state,

gt0_txout_n[0:2] 		Output async Channel 0 10Gbps differential output Lane 0,1, and 2 to DLPC964 Controller
gt1_txout_p[0:2]
Output async Channel 1 10Gbps differential output Lane 0,1, and 2 to DLPC964 Controller
gt2_txout_p[0:2]
Output async Channel 2 10Gbps differential output Lane 0,1, and 2 to DLPC964 Controller
gt3_txout_p[0:2]
Output async Channel 3 10Gbps differential output Lane 0,1, and 2 to DLPC964 Controller
gt0_refclkin_p
Input async Channel 0 100MHz differential transceiver external reference clock from a low-jitter oscillator.
gt1_refclkin_p
Input async Channel 1 100MHz differential transceiver external reference clock from a low-jitter oscillator.
gt2_refclkin_p
Input async Channel 2 100MHz differential transceiver external reference clock from a low-jitter oscillator.
gt3_refclkin_p
Input async Channel 3 100MHz differential transceiver external reference clock from a low-jitter oscillator.
gt_txpostcursor_in[4:0] Input async

Transceiver post-cursor TX pre-emphasis control and is set to "00000" for TI EVM hardware.

Customer must perform IBERT eyescan to determine the best setting for the hardware.
gt_txdiffctrl_in[3:0] Input async

Transceiver TX driver swing control and is set to "1000" (807mV differential peak to peak swing) for TI EVM hardware.

Customer must perform IBERT eyescan to determine the best setting for the hardware.
gt_txmaincursor_in[6:0] Input async Transceiver main-cursor TX control and is set to "0000000" for TI EVM hardware. Customer must perform IBERT eyescan to determine the best setting for the hardware.
gt_txprecursor_in[4:0] Input async Transceiver pre-cursor TX pre-emphasis control and is set to "00000" for TI EVM hardware. Customer must perform IBERT eyescan to determine the best setting for the hardware.
clk_user Output clk_user 156.25MHz clock for user interface to Aurora cores.
clk_user_not_locked_uo Output async When high, indicates clk_user is not locked, and can be used to keep user logics in reset state if clk_user loose lock in power-up or system reset condition.
gt(0,1,2,3)_s_axi_tx_tdata[191:0] Input clk_user DMD pixel data to be transmitted across the Aurora links.
gt(0,1,2,3)_s_axi_tx_tvalid Input clk_user User logics asserted this signal high to indicate to Aurora core the DMD pixel data is valid to transmit. Aurora cores ignore data if tvalid is low. Refer to the Xilinx app note for the AXI4-stream tready signal behavior.
gt(0,1,2,3)_s_axi_tx_tready Output clk_user Aurora cores assert this signal high when DMD pixel data is accepted. Deasserted when pixel data are ignored, ie. cores are not ready to accept data. Refer to the Xilinx app note for the AXI4-stream tready signal behavior.
gt(0,1,2,3)_s_axi_user_k_tx_tdata[191:0] Input clk_user User-k control word data to be transmitted across the Aurora links.
gt(0,1,2,3)_s_axi_user_k_tx_tvalid Input clk_user User logics asserted this signal high to indicate to Aurora core th user-k control word data is valid to transmit. Aurora core ignore data if tvalid is low.
gt(0,1,2,3)_s_axi_user_k_tx_tready Output clk_user Aurora core asserts this signal high when user-k control word data are accepted. Deasserted when data are ignored, ie. cores not ready to accept data.
gt(0,1,2,3)_hard_err Output clk_user Asserted high when Aurora core detects a hard error. Refer to the Xilinx app note Table 2-13 for the hard error definition.
gt(0,1,2,3)_soft_err Output clk_user Asserted high when Aurora core detects a soft error. Refer to the Xilinx app note Table 2-13 for the soft error definition.
gt(0,1,2,3)_channel_up Output clk_user Asserted high after Aurora cores complete the channel initialization sequence.
gt(0,1,2,3)_lane_up[2:0] Output clk_user Asserted high for each lane upon successful lane initialization with each bit representing one lane.
tp_gt0_pll_lock Output async

Asserted high when Aurora channel 0 tx_out_clk is stable. As stated in earlier section, channel 0 tx_out_clk is used to generate clk_user.

tx_out_clk is 312.5MHz out of the Aurora transceiver and divided by two to form clk_user of 156.25MHz.