DLPU133 March   2024 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments

3.2.3 Pattern Mode

Note: When changing pattern mode, follow the steps in Section 3.2.4 below

The pattern mode register allows the user to experiment with the various DLPC964 modes of operation. The table below goes over all the available pattern modes:

Mode Number Value Name Settings Notes
1 0x0 Global Mode
  • Global Reset Mode (0x3)
  • Normal Load Type (0x0)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)
 In global reset mode, all enabled blocks are loaded with data sequentially. Once all blocks have been loaded, the MCP_Start signal resets all the blocks at the same time.
2 0x1 Quad Mode
  • Quad Reset Mode (0x2)
  • Normal Load Type (0x0)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)
 In quad reset mode, 4 blocks are loaded sequentially. Once the 4 blocks in a group have been loaded, the MCP_Start signal issues a reset to the 4 blocks in that group at the same time.
Note: There are 4 "groups" of blocks in Quad reset mode. Blocks 0-3, 4-7, 8-11, and 12-15. All blocks in a group must be enabled or disabled.
3 0x2 Double Mode
  • Double Reset Mode (0x1)
  • Normal Load Type (0x0)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)
 In double reset mode, 2 blocks are loaded sequentially. Once the 2 blocks in a group have been loaded, the MCP_Start signal issues a reset to the 2 blocks in that group at the same time.
Note: There are 8 "groups" of blocks in Double reset mode. Blocks 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, 14-15. All blocks in a group must be enabled or disabled.
4 0x3 Single Mode
  • Single Reset Mode (0x0)
  • Normal Load Type (0x0)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)
 In single reset mode, a single block is loaded at a time and once the DLPC964 has loaded the DMD with the data sent, the MCP_Start signal resets that single block.
5 0x4 Global Clear Mode
  • Global Reset Mode (0x3)
  • Clear Load Type (0x1)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)

This mode shows how the Clear block load type is used in the DLPC964 system.

A clear load type does not require any data because the block puts all the mirrors in the off state (0). Because the clear load type does not have any data to be sent following, the command valid signal is not needed so only the dmd load signal is sent.

The MCP_Start signal follows the same pattern as Global Mode.
6 0x5 Global Set Mode
  • Global Reset Mode (0x3)
  • Set Load Type (0x2)
  • Load2 Disabled (0x0)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)

This mode shows how the Set block load type is used in the DLPC964 system.

A set load type does the opposite of the clear load type and also does not require any data. The set load type sets all all the mirrors in the on state (1). Just like the clear load type, there is no need for the command valid signal, only the dmd load signal.

The MCP_Start signal follows the same pattern as Global Mode.
7 0x6 Global Load2 Mode
  • Global Reset Mode (0x3)
  • Normal Load Type (0x0)
  • Load2 Enabled (0x1)
  • Fast Mode Enabled (0x1)
  • Total Rows Loaded (136 = 0x88)

Enabling the load2 operation tells the DMD to load 1 line of data received into 2 rows of the DMD.

The role of the DLPC964 Apps FPGA during a Load2 operation is to make sure that at most 68 lines are sent over the Aurora HSS channels and that the number of rows enabled in the user-k control parameter is halved as well.
8 0x7 Single Slow Mode
  • Single Reset Mode (0x0)
  • Normal Load Type (0x0)
  • Load2 Disabled (0x0)
  • Slow Mode Enabled (0x0)
  • Total Rows Loaded (136 = 0x88)

Slow mode (or disabling the fast mode) causes the DLPC964 Apps FPGA to send data across a single channel only (4x 10Gbps lanes compared to 12x).

To do this, each segment of a block must be sent sequentially across 1 channel instead of parallel. The segments must be sent in the following order: D (0x3) → C (0x2) → B (0x1) → A (0x0). Once all 4 segments are sent, the MCP_Start signal can be issued.

The MCP_Start signal behaves the same as in Single Mode.