DLPU133A March   2024  – February 2025 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 2.1 Get Started
    2. 2.2 Features
    3. 2.3 Assumptions
    4. 2.4 Apps FPGA Hardware Target
  5. 2Apps FPGA Modules
    1. 3.1  Apps FPGA Block Diagram
    2. 3.2  BPG Module
    3. 3.3  BRG Module
      1. 3.3.1 Start Signal Logic
      2. 3.3.2 Delay Needed Logic
      3. 3.3.3 Blocks Sent/Loaded Logic
    4. 3.4  BRG_ST Module
    5. 3.5  PGEN Module
    6. 3.6  PGEN_MCTRL Module
    7. 3.7  PGEN_SCTRL Module
    8. 3.8  PGEN_PRM Module
    9. 3.9  PGEN_ADDR_ROM
    10. 3.10 HSSTOP Module
    11. 3.11 SSF Module
    12. 3.12 ENC Module
    13. 3.13 Xilinx IP
      1. 3.13.1 PGEN_SPBROM_v3
      2. 3.13.2 MAINPLL
      3. 3.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 3.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 3.14 Reference Documents
    15. 3.15 DLPC964 Apps FPGA IO
    16. 3.16 Key Definitions
  6. 3Functional Configuration
    1. 4.1 Blocks Enabled
    2. 4.2 Pattern Cycle Enable
      1. 4.2.1 North/South Flip
      2. 4.2.2 TPG Patterns
      3. 4.2.3 Pattern Mode
      4. 4.2.4 Switching Modes
      5. 4.2.5 Changing the BPG Patterns
  7. 4Appendix
    1. 5.1 Vivado Chipscope Captures
    2. 5.2 DLPC964 Apps Bitstream Loading
      1. 5.2.1 Loading Bitstream onto FPGA
      2. 5.2.2 Loading Bitstream onto Flash
    3. 5.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 5.3.1 Theory of Operation
      2. 5.3.2 Overview
      3. 5.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 5.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 5.3.3.2  Configure Core Options
        3. 5.3.3.3  Lane Configurations
        4. 5.3.3.4  Shared Logic Options
        5. 5.3.3.5  Generate Example Design Files
        6. 5.3.3.6  RTL File List
        7. 5.3.3.7  Single Channel 3 Lanes Aurora Core RTL Wrapper
        8. 5.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 5.3.3.9  Block Start with Block Control Word
        10. 5.3.3.10 Block Complete with DMDLOAD_REQ
        11. 5.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 5.3.3.12 Single Channel Transfer Mode
        13. 5.3.3.13 DMD Block Array Data Mapping
        14. 5.3.3.14 Xilinx IBERT
  8. 5Abbreviations and Acronyms
  9. 6Related Documentation from Texas Instruments
  10. 7Revision History

2.15 DLPC964 Apps FPGA IO

Signal Name Input/ Output Description

refclk_ui_p

refclk_ui_n

 INPUT Fixed 200MHz LVDS reference clock generated from DLPC964 Apps FPGA (Reference from VC-707: U51).
reset_ui INPUT Push button (Reference from VC-707: SW7) to reset the DLPC964 Apps FPGA.
irqz INPUT PBC Interrupt from DLPC964 Controller.
running OUTPUT Goes to LED0 (Reference from VC-707 GPIO_LED_0) on DLPC964 Apps FPGA to signal when out of reset.
C964_init_done INPUT Input from the DLPC964 that tells the DLPC964 Apps FPGA to be pulled out of reset.
wdt_enablez OUTPUT Watchdog Timer set to '1' when in operation
rxlpmen OUTPUT Set to 0 for low power mode equalization. Refer to the Xilinx App note for more information.
ext_hssi_rst OUTPUT Signal that resets the DLPC964 HSSI Interface.
hssi_bus_err INPUT From DLPC964 that signals there was a sync error when loading last block onto DLPC964.
hssi_rst_act INPUT From DLPC964 to tell Apps DLPC964 the HSSI is being reset
load2 OUTPUT Used during DLPC964 init process to setup DMD in load2 mode.
blkmode[1:0] OUTPUT Used during DLPC964 init process to setup DMD superblock mode.
blkaddr[4:0] OUTPUT Block (or superblock) address the issued mcp_start is sent.
mcp_start OUTPUT Signals the DLPC964 to load whatever data was sent onto the DMD.
mcp_active[3:0] INPUT From the DLPC964 to signal when the DMD is loading data onto the DMD. Only 4 loads can happen at once.
blkloadz INPUT From the DLPC964 to signal when the block data sent is done being loaded and ready to be sent to the DMD.
dmdload_req OUTPUT Signals the DLPC964 to load the block recently sent into the controller into the DMD.

gtrx_ch0_refclk_p/n

gtrx_ch1_refclk_p/n

gtrx_ch2_refclk_p/n

gtrx_ch3_refclk_p/n

 INPUT Reference clock from the DLPC964 for each of the Aurora Transmit channels (GTX Channel 0 - 3).
ch0_gtx_p/n[2:0] OUTPUT

Aurora 10Gbps Transmit channel 0.

User-k data is sent across channel 0 ONLY along with the data.

When slow mode is enabled (pbc_bpg_normal_mode_en = 0), channel 0 is the only channel sending data.
ch1_gtx_p/n[2:0] OUTPUT Aurora 10Gbps Transmit channel 1.
ch2_gtx_p/n[2:0] OUTPUT Aurora 10Gbps Transmit channel 2.
ch3_gtx_p/n[2:0] OUTPUT Aurora 10Gbps Transmit channel 3.
i2c_sda INOUT I2C Data line shared with the DLPC964.
i2c_scl INOUT I2C Clock line shared with DLPC964.
fmc_gpio[6:0] INOUT GPIO between the DLPC964 Apps FPGA and DLPC964.
led OUTPUT Goes to LED1 (Reference from VC-707 GPIO_LED_1) on DLPC964 Apps FPGA to signal when BPG is enabled.
testmux_uo[15:0] INOUT Debug mux for the DLPC964 Apps FPGA.