SBAA491A November   2021  – April 2022 PCM5120-Q1 , PCM6120-Q1 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Dynamic Range Enhancer
  4. 3 Dynamic Range Compressor
  5. 4 PGA Anti-Saturation
  6. 5 High Pass Filter
  7. 6 DRE/DRC Parameters
  8. 7 Sample Rate Support
  9. 8 Example
  10. 9 References
  11. 10Revision History

4 PGA Anti-Saturation

The DRE and DRC algorithms have a feature to prevent saturation of the PGA for bounded input signals. The input signal level is compressed to avoid clipping when channel gain (PGA gain) is greater than 0 dB. This feature can be enabled using the EN_AVOID_CLIP bit of DSP_CFG1 register (page = 0x00, address = 0x6C).

Table 4-1 PGA Anti-Saturation Selection Using DSP_CFG1 Register
BIT FIELD TYPE RESET DESCRIPTION
0 EN_AVOID_CLIP R/W 0b Anti clippler when channel gain > 0 dB and either of DRE, DRC or AGC mode enabled. 0d = Channel gain is maintained as per user programmed value.
1d = Signal level is compressed to avoid clipping when channel gain > 0 dB and signal level crosses programmed threshold setting set in page-4.

A typical example application for PGA anti-saturation feature occurs when some constant analog programmable gain (C0 dB) is configured along with DRE or DRC. Increasing the input signal level beyond a certain level (-C0 dB) causes the output of the PGA to saturate which is detrimental to the performance of the analog circuitry. With PGA anti-saturation feature enabled, the PGA output does not saturate even if input signal level increases beyond – C0 dB level because the PGA gain is reduced and the residual gain is applied on the digital side. The overall channel gain remains unchanged.