Condenser Microphone: Single Ended DC Coupled Input

The circuit below is of a DC coupled condenser microphone. A MicBias of 3.3 V is setup and a biasing resistor of 3 k is used setting up a Static DC level of 1.375 V on INxP pin. AVDD is 3.3 V. Sound signals picked up by the microphone create variations over this static DC bias.

The high pass filter is used to remove the static DC level from the digital output. The digital output capture shown below is for a 1-Vrms input riding over a DC bias of 1.375 V.

Figure 4-18 Single Ended DC Coupled Microphone Circuit

Figure 4-19 Digital Output Capture (Vin = 1 VRMS)

Input Timing: 32 bit TDM, FSYNC = 48-kHz, BCLK = 12.288 Mhz.
w 9c 00 00 # Select Page 0
w 9c 01 01 # Reset Device
# 1mS Delay.
w 9c 00 00 # Select Page 0
w 9c 02 81 # Wake up and Enable AREG
w 9c 05 15 # ASI Channel configuration
w 9c 0c 01
w 9c 0d 02
w 9c 0e 03
w 9c 3b 60 # MicBias = 3.3 V
w 9c 3c b4 # Channel 1 configuration
w 9c 41 b4 # Channel 2 configuration
w 9c 74 c0 # input and output Configuration
# High pass filter coefficients
w 9c 49 e6
w 9c 4a 48
w 9c 4b c6
w 9c 4c 80
w 9c 4d 19
w 9c 4e b7
w 9c 4f 3a
w 9c 50 7f
w 9c 51 cc
w 9c 52 91
w 9c 53 8b
w 9c 00 06 # Select page 6
w 9c 1d 04
w 9c 1e b0
w 9c 7e 2d
w 9c 00 00 # Power up/down
w 9c 75 E0

Condenser Microphone: Differential DC Coupled Input

The circuit below is of a differential DC-coupled condenser microphone. A mic bias of 3.3 V is setup and biasing resistors R of 1.1 K is used setting up a static DC level of 2.25-V on INxP and 0.75 V on INxM pin. AVDD is 3.3 V. Sound signals picked up by the microphone create variations over these static DC bias levels.

The high pass filter is used to remove the static DC level from the digital output. The digital output capture shown below is for a 1-Vrms differential input.

Figure 4-20 Differential DC Coupled Circuit for Condenser Mic

Figure 4-21 Digital Capture (Analog Differential Input of 1 Vrms)

Input Timing: 32 bit TDM, FSYNC = 48-kHz, BCLK = 12.288 Mhz.
w 9c 00 00 #Select Page 0
w 9c 01 01 # Reset Device
# 1mS Delay
w 9c 00 00 # Select Page 0
w 9c 02 81 # Wake up and Enable AREG
w 9c 05 15
w 9c 0c 01 # ASI Channel configuration
w 9c 0d 02
w 9c 0e 03
9c 3b 60 # MicBias = 3.3 V
w 9c 3c 90 # Channel 1 configuration
w 9c 41 90 # Channel 2 configuration
w 9c 74 c0 # input and output Configuration
w 9c 00 04 # Select page 4
# High pass filter coefficients
w 9c 49 e6
w 9c 4a 48
w 9c 4b c6
w 9c 4c 80
w 9c 4d 19
w 9c 4e b7
w 9c 4f 3a
w 9c 50 7f
w 9c 51 cc
w 9c 52 91
w 9c 53 8b
w 9c 00 06 # Select page 6
w 9c 1d 04
w 9c 1e b0
w 9c 7e 2d
w 9c 00 00 # Select page 0
w 9c 75 E0