Figure 3-4 shows the schematic of the phase current sense subsystem using the functionally isolated modulator AMC0106M05 (U8) with a ±50mV linear input voltage range, and a 1mΩ, 3W shunt (R39). The 1mΩ shunt value determines that the linear input range is ±50A. The AMC0106M05 has a ±64mV clipping range, therefore the maximum current range is ±64A. The power dissipation in the shunt at 35A_RMS is 1.25W.

Figure 3-4 AMC0106M05 Schematic Using the LMG2100R44 Bootstrap Supply

The differential anti-aliasing low-pass filter (R41=10Ω, R45=10Ω, C61=10nF) in front of the isolated modulator has a cut-off frequency of 795kHz and helps to improve signal-to-noise performance of the signal path. The purpose of the low-pass filter is to attenuate high-frequency input noise below the desired noise level of the measurement. Without the input filter, noise close the sampling frequency (f_CLKIN), or multiples of the sampling frequency, is aliased to low-frequencies by the delts-sigma modulator and passes through the digital low-pass filter. The capacitors C65=1nF and C66=1nF are optional and improve common-mode input voltage rejection at frequencies above 10MHz. C65 and C66 are sized 10x smaller than C61. For best performance, make sure C65 and C66 values match better than 5%. Mismatch between C65 and C66 causes differential input error during common-mode transients. NP0-type capacitors offer low temperature drift and are preferred for common-mode filtering.

The analog supply AVDD is decoupled with a 100nF capacitor, C56. AVDD is supplied by one of two bootstrap supply options. The default option leverages the LMG2100R044 bootstrap supply with C40=4.7µF and a current limit resistor R15=3Ω. The bootstrap diode is integrated into the LMG2100R044 GaN-FET. The AMC0106M05 typically draws 6.6mA from the AVDD supply. This configuration allows for operating at PWM frequencies from 10kHz to 100kHz with a maximum continuous duty cycle of a round 95%. Refer to the test results for more details.

The resistor R14=0Ω is a configuration option to use a separate bootstrap supply. The resistor consists of an ultra fast rectifier diode D1, a 4.7µF capacitor C57 and a 3Ω current limit resistor R34, not populated with the default option.

The digital supply DVDD is decoupled with the capacitors C58=2.2µF and C59=100nF. A series 0Ω resistor (R37) is a placeholder for an optional ferrite bead. Ferrite beads help reduce coupling of transient load current spikes into the 3.3V plane and therefore improve EMI performance.

A 50Ω series line termination resistor R40 at the AMC0106M05 DOUT pin improves signal integrity. An optional capacitor C62=33pF allows for slew rate reduction of the modulator output bit-stream signal to further reduce EMI. For more information on improving the digital interface from an isolated modulator to a microcontroller refer to Achieving Better Signal Integrity with Isolated Delta-Sigma Modulators in Motor Drives and Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs.

Figure 3-5 shows the layout of the board with the shunt (R39) on the top-side of the PCB and the AMC0106M05 (U8) on the bottom side of the PCB. The shunt’s terminals are connected to through a Kelvin connection to the two series input resistors R41 and R45 on the top layer. On the other side of the resistors, both signals are connected through vias to the corresponding input pins of the AMC0106M05 (INN and INP) that is placed on the bottom layer. The decoupling capacitor C61 is placed as close as possible to the input pins INN and INP and on the same layer as the AMC0106M05. The shunt terminal facing to the U3 LMG2100R044 GaN-FET's switch node (Ph-C) is connected through a via to the analog GND (AGND) pin of the AMC0106M05. The AVDD decoupling cap C56 is placed on the bottom layer close to the AVDD pin and connected to the AGND trace on the same layer.

Figure 3-5 AMC0106M05 Top and Bottom Layer PCB Layout