SBAA666 February   2025 AMC0106M05 , AMC0106M25

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Challenges
  6. 3Design Approach
    1. 3.1 AMC0106Mxx Functionally Isolated Modulators
    2. 3.2 Circuit Design and Layout
    3. 3.3 Sinc3 Filter Design
  7. 4Test and Validation
    1. 4.1 Test Setup
    2. 4.2 Digital Interface
    3. 4.3 DC Accuracy, Noise, and Effective Number of Bits
    4. 4.4 PWM Rejection
      1. 4.4.1 DC Phase Current Measurement Over One PWM Cycle
      2. 4.4.2 AC Phase Current Measurement at 100kHz PWM
    5. 4.5 Bootstrap Supply Validation and AVDD Ripple Rejection Tests
      1. 4.5.1 LMG2100R044 Bootstrap Supply With Low Voltage-Ripple
      2. 4.5.2 Discrete Bootstrap Supply With High Voltage-Ripple
  8. 5Summary
  9. 6References

4.2 Digital Interface

Figure 4-2 shows the timing of the digital interface. The AMC0106M05 is clocked at 20MHz. A new data bit is output on the rising edge of clock. The typical delay between the rising edge of clock to the rising (or falling) edge of data is 22ns. For information on how to optimize the setup and hold timing with the microcontroller, refer to Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs.

Digital Interface Timing Figure 4-2 Digital Interface Timing