5 RF Repeater System Without FPGA/ASIC

Traditionally, the typical RF input to RF output loopback through integrated RF transceiver has to go through the following path as shown in the signal chain for a typical repeater system (see Figure 5-1).

RF input to RX DDC chain, through the JESD204 TX chain, externally through some PCB routing (either through the FPGA or directly JESD204 TX to JESD204 RX traces), through the JESD204 RX chain, to the TX DUC chain and then up convert to the RF output.

Although the FPGA provides additional signal processing enhancement for the DAS or repeater system such as additional digital filtering and potentially ISI cancellation (for example, inter symbol cancellation), the FPGA is the main cost driver for the system, and potentially impact overall power consumption of the system. Moreover, the industrial standard interface between RF transceiver is the JESD204 standard with serialized interface. The interface between the FPGA and RF transceiver adds latency to the repeater system.

As shown in Figure 5-1, The AFE7769D offers internal RX DDC to TX DUC direct loopback. As the RX DDC chain’s down conversion signal feeds directly into the TX DUC upconversion chain, the entire signal path has reduced latency.

As shown in Figure 5-2, in addition to the direct RX DDC to TX DUC direct loopback, the integrated digital pre-distortion (DPD) capability of the AFE7769D can linearize power amplifiers in the transmitter system. Integrating the DPD processing logic to the RF transceiver further reduces the cost and power consumption of the system.