SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

7.3.3.4 LVDS Interface Input Strobe

The LVDS strobe can be provided on either the dedicated strobe pin or the LSB of the data pins. The strobe can be provided at any multiple of 4 LVDS clocks, which is equivalent to 8 input samples per LVDS bus per DAC. The strobe must be provided on the rising edge of the LVDS clock and coincide with the data captured on that edge. The LVDS strobe is used to reset the FIFO write pointer for each LVDS bus.

When the strobe is provided on the LSB, the actual pin that is used is determined by the LVDS input width set by LVDS_RESOLUTION.

When using the LSB for the strobe pin, a couple of LVDS clocks are required to switch between using the LSB for strobe and using it for data. The user should make sure the data on this bit is held at zero during this transition. The dedicated strobe input needs to be tied low in order to use a strobe on the LSB. If using LSB_SYNC instead of the SYNC pin to switch the LSB between strobe and data, the SYNC input must be tied high.

When the LSB is being used as a strobe (either SYNC is low or register LSB_SYNC=1), the LSB of the input data passed to the datapath will be zero.

Note that there is only one FIFO_DLY setting for the chip. When the FIFO is aligned to the LVDS strobe it aligns to the strobe for LVDS bus 0 (if bus 0 is enabled). Otherwise it aligns to bus 2. This means that in dual DAC mode, it is required that the strobes for the LVDS buses used for DACB must be aligned to the strobes for the LVDS buses for DACA within the FIFO tolerance.