SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics - Power Consumption

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Dual channel, NRZ mode, fCLK = 3.2 GHz, fDATA = 3.2 Gsps, LVDS_MODE = 1 38 40 mA
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 -90 -84
IVDDA 1.0-V supply current for VDDA 0.15 0.4
IVDDCLK18 1.8-V combined supply current for VDDCLK18 and VDDSYS18 8.0 10
IVDDCLK 1.0-V combined supply current for VDDHAF, VDDL2B, VDDL2A and VDDCLK10 597 800
IVDDIO 1.8-V supply current for VDDIO 7 10
IVDDE 1.0-V combined supply current for VDDEB and VDDEA 242 350
IVDDDIG 1.0-V supply current for VDDDIG 319 800
PDIS Total power dissipation 1.49 1.95 W
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Dual channel, RF mode, fCLK = 3.2 GHz, fDATA = 3.2 Gsps, LVDS_MODE = 1 38 40 mA
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 -90 -84
IVDDA 1.0-V supply current for VDDA 0.15 0.4
IVDDCLK18 1.8-V combined supply current for VDDCLK18 and VDDSYS18 8.0 10
IVDDCLK 1.0-V combined supply current for VDDHAF, VDDL2B, VDDL2A and VDDCLK10 597 800
IVDDIO 1.8-V supply current for VDDIO 7 10
IVDDE 1.0-V combined supply current for VDDEB and VDDEA 242 350
IVDDDIG 1.0-V supply current for VDDDIG 320 800
PDIS Total power dissipation 1.49 1.95 W
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Dual channel, 2xRF mode, fCLK = 6.4 GHz (double rate DAC), fDATA = 3.2 Gsps, LVDS_MODE = 1 38 40 mA
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 -90 -84
IVDDA 1.0-V supply current for VDDA 0.15 0.4
IVDDCLK18 1.8-V combined supply current for VDDCLK18 and VDDSYS18 7.8 10
IVDDCLK 1.0-V combined supply current for VDDHAF, VDDL2B, VDDL2A and VDDCLK10 945 1200
IVDDIO 1.8-V supply current for VDDIO 6.5 10
IVDDE 1.0-V combined supply current for VDDEB and VDDEA 400 500
IVDDDIG 1.0-V supply current for VDDDIG 400 800
PDIS Total power dissipation 2.1 2.95 W
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Single channel, RF mode, fCLK = 6.4 GHz, fDATA = 6.4 Gsps, LVDS_MODE = 2 24 30 mA
IVEE –1.8-V combined supply current for VEEA– and VEEB– -52 -48
IVDDA 1.0-V supply current for VDDA 0.15 0.4
IVDDCLK18 1.8-V combined supply current for VDDCLK18 and VDDSYS18 7.8 10
IVDDCLK 1.0-V combined supply current for VDDHAF, VDDL2B, VDDL2A and VDDCLK10 935 1200
IVDDIO 1.8-V supply current for VDDIO 6.5 10
IVDDE 1.0-V combined supply current for VDDEB and VDDEA 365 500
IVDDDIG 1.0-V supply current for VDDDIG 420 800
PDIS Total power dissipation 2.05 2.75 W
IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Dual channel, RF mode, fCLK = 6.4 GHz, fDATA = 6.4 Gsps, LVDS_MODE = 2, DAC A outputting data from LVDS interface and DAC B operating as DDS 38 40 mA
IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 -90 -84
IVDDA 1.0-V supply current for VDDA 0.15 0.4
IVDDCLK18 1.8-V combined supply current for VDDCLK18 and VDDSYS18 7.8 10
IVDDCLK 1.0-V combined supply current for VDDHAF, VDDL2B, VDDL2A and VDDCLK10 950 1200
IVDDIO 1.8-V supply current for VDDIO 6.5 10
IVDDE 1.0-V combined supply current for  VDDEB and VDDEA 400 525
IVDDDIG 1.0-V supply current for VDDDIG 697 1050
PDIS Total power dissipation 2.27 3.3 W
PDIS Total power dissipation MODE = 0b11, SHUNTREG_EN Register (Offset = 1A0h-1A1h) = 0x0000 148 mW