SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics - DC Specifications

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, single channel (MODE2) at 6.4 GSPS, RF mode, IOUTFS = 20.5mA, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
BITS DAC core resolution(1) 16 bits
DNL Differential nonlinearity LVDS input with 12-bit resolution (1 LSB = Fullscale/4096) ±0.6 LSB
INL Integral nonlinearity LVDS input with 12-bit resolution (1 LSB = Fullscale/4096) ±0.9 LSB
DAC ANALOG OUTPUT (IOUTA+, IOUTA–, IOUTB+, IOUTB–)
POUTFS Output power DACFS = 0xF, NRZ mode, 6.4 Gsps, fOUT = 397 MHz, measured into 100-Ω load(5)(4) 1.4 dBm
IFS Switched full scale output current(2) 3.6-kΩ resistor from RBIAS to AGND, COARSE_CUR_A/B = 0xF and FINE_CUR_A/FINE_CUR_B = 0x1F 20.5 mA
3.6-kΩ resistor from RBIAS to AGND, COARSE_CUR_A/B = 0x0 and FINE_CUR_A/FINE_CUR_B = 0x00 5.2
IFSDRIFT Full scale output current temperature drift 3.6-kΩ resistor from RBIAS to AGND, COARSE_CUR_A/B = 0xF and FINE_CUR_A/FINE_CUR_B = 0x1F 0.6 uA/℃
23 PPM/℃
VCOMP Output compliance voltage range Meaured from VOUTA+, VOUTA–, VOUTB+ or VOUTB– to AGND 1.3 2.3 V
COUT Output capacitance Single-ended capacitance to ground 0.04 pF
RTERM Output differential termination resistance 109 Ω
RTERMDRIFT Output differential termination resistance temperature coeff -0.13 mΩ/℃
-133 PPM/℃
CLOCK AND SYSREF INPUTS (CLKIN+, CLKIN-, SYSREF+, SYSREF-)
RT Internal differential termination resistance 107 Ω
VCM Input common mode voltage 0.5 V
CIN Internal differential input capacitance 0.5 pF
REFERENCE OUTPUT (EXTIO)
VREF Reference output voltage 0.9 V
VREF-DRIFT Reference output voltage drift over temperature ±34 ppm/°C
IREF Maximum reference output current sourcing capability 100 nA
LVDS INTERFACE (DAx±, DBx±, DCx±, DDx±, DxSTR±, DCLKx±)
RT Internal differential termination resistance 115 Ω
CMOS INTERFACE (SCLK, SCS, SDI, SDO, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC)
IIH High level input current High level input current(6) 200 uA
IIL Low level input current Low level input current(6) -200 uA
VIH High level input voltage SCLK, SCS, SDI, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC, TESTMODE, TXENABLE(3) 0.7 x
VDDIO18		 V
VIL Low level input voltage SCLK, SCS, SDI, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC, TESTMODE, TXENABLE(3) 0.3 x
VDDIO18		 V
CI Input capacitance Input capacitance 2 pF
VOH High level output voltage ILOAD = –400 uA 1.55 V
VOL Low level output voltage ILOAD = 400 uA 0.25 V
TEMPERATURE SENSOR
Res Resolution 8 bits
Range Digital Range -64 127 ℃
TERROR Temperature Error TA = 25℃, device powered down except for temperature sensor and SPI interface ±5 ℃
(1) When using LVDS input, the resolution is limited by the LVDS interface to 12-bits. 16-bits only applies when using the NCO.
(2) In addition to the switched full scale output current, each output (VOUTA+, VOUTA-, VOUTB+, VOUTB-) has a fixed output current of ~ 3mA at a coarse DAC setting of 15.
(3) Measured to DGND.
(4) See DAC Output Modes for information on the frequency response of different DAC output modes. Output power vs frequency for different modes relative to NRZ mode at low frequency is shown in Figure 6-3  through Figure 6-8
(5) A 100Ω load is equivalent to a 2:1 with 50Ω single ended load
(6) With no IO supply voltage offset in connecting device.