The host controller can operate the ADS9120 at the desired throughput by interleaving the conversion cycles and the data transfer frames.

The cycle time of the device, t_cycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, t_resp, is the time difference between the host controller initiating a conversion C and the host controller receiving the complete result for conversion C.

Figure 6-12 shows three conversion cycles, C, C+1, and C+2. Conversion C is initiated by a CONVST rising edge at the t = 0 time and the conversion result becomes available for data transfer at the t_conv time. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of the conversion C+1 (that is, before the t_cycle + t_conv time).

To achieve the rated performance specifications, the host controller must ensure that no digital signals toggle during the quiet acquisition time (t_{qt_acq}) and quiet aperture time (t_{d_cnvcap}), as shown in Figure 6-12. Any noise during t_{d_cnvcap} can negatively affect the result of the ongoing conversion whereas any noise during t_{qt_acq} can negatively affect the acquisition of the subsequent sample (and hence it's conversion result).

Figure 6-12 Data Transfer Zones

This architecture allows for two distinct time zones (zone1 and zone2) to transfer data for each conversion. Zone1 and zone2 for conversion C are defined in Table 6-3.

Table 6-3 Data Transfer Zones Timing

ZONE	STARTING TIME	ENDING TIME
Zone1 for conversion C
Zone2 for conversion C

The response time includes the conversion time and the data transfer time, and is thus a function of the data transfer zone selected.

Figure 6-13 and Figure 6-14 illustrate interleaving of three conversion cycles (C, C+1, and C+2) with three data transfer frames (F, F+1, and F+2) in zone1 and in zone2, respectively.

Figure 6-13 Zone1 Data Transfer

Figure 6-14 Zone2 Data Transfer

To achieve cycle time, t_cycle, the read time in zone1 is given by Equation 5:

Equation 5.

For an optimal read frame, Equation 5 results in an SCLK frequency given by Equation 6:

Equation 6.

Then, the zone1 data transfer achieves a response time defined by Equation 7:

Equation 7.

As an example, when operating the ADS9120 at the full throughput of 2.5 MSPS, the host controller can achieve a response time of 400 ns provided that the data transfer in zone1 is completed within 85 ns. However, to achieve this response time, the SCLK frequency must be greater than 188 MHz.

Note that the device does not support such high SCLK speeds.

Data transfer in zone2 can acheive lower SCLK speeds for the same cycle time. The read time in zone2 is given by Equation 8:

Equation 8.

For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:

Equation 9.

Then, the zone2 data transfer achieves a response time defined by Equation 10:

Equation 10.

As an example, the host controller can operate the ADS9120 at the full throughput of 2.5 MSPS using zone2 data transfer with a 44 MHz SCLK (and a read time of 365 ns). However, zone2 data transfer results in a response time of nearly 800 ns.

There is no upper limit on t_read-Z1 and t_read-Z2, however, any increase in these read times will increase the response time and may increase the cycle time.

For a given cycle time, the zone1 data transfer clearly achieves faster response time but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7), whereas the zone2 data transfer clearly requires a lower SCLK speed but supports slower response time (as evident from Equation 8, Equation 9, and Equation 10).