SBAS710B September   2016  – April 2026 ADS9120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Conversion Cycle
    7. 5.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 5.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 5.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 5.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Converter Module
        1. 6.3.1.1 Sample-and-Hold Circuit
        2. 6.3.1.2 External Reference Source
        3. 6.3.1.3 Internal Oscillator
        4. 6.3.1.4 ADC Transfer Function
      2. 6.3.2 Interface Module
    4. 6.4 Device Functional Modes
      1. 6.4.1 RST State
      2. 6.4.2 ACQ State
      3. 6.4.3 CNV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 6.5.3 Data Transfer Protocols
        1. 6.5.3.1 Protocols for Configuring the Device
        2. 6.5.3.2 Protocols for Reading From the Device
          1. 6.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 6.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 6.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 6.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 6.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 6.5.4 Device Setup
        1. 6.5.4.1 Single Device: All multiSPI™ Options
        2. 6.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 6.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 6.5.4.4 Multiple Devices: Star Topology
    6. 6.6 Register Maps
      1. 6.6.1 Device Configuration and Register Maps
        1. 6.6.1.1 PD_CNTL Register (address = 010h)
        2. 6.6.1.2 SDI_CNTL Register (address = 014h)
        3. 6.6.1.3 SDO_CNTL Register (address = 018h)
        4. 6.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 ADC Input Driver
      2. 7.1.2 Input Amplifier Selection
      3. 7.1.3 Charge Kickback Filter
      4. 7.1.4 ADC Reference Driver
    2. 7.2 Typical Application
      1. 7.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
  9. 8 Power-Supply Recommendations
    1. 8.1 Power-Supply Decoupling
    2. 8.2 Power Saving
      1. 8.2.1 NAP Mode
      2. 8.2.2 PD Mode
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Signal Path
      2. 9.1.2 Grounding and PCB Stack-Up
      3. 9.1.3 Decoupling of Power Supplies
      4. 9.1.4 Reference Decoupling
      5. 9.1.5 Differential Input Decoupling
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2.5 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C, unless otherwise noted.
All typical values are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range
(AINP – AINM)(1)		 –VREF VREF V
VIN Absolute input voltage
(AINP and AINM to REFGND)		 –0.1 VREF + 0.1 V
VCM Common-mode voltage range
(AINP + AINM) / 2		 (VREF / 2) – 0.1 VREF / 2 (VREF / 2) + 0.1 V
CIN Input capacitance In sample mode 60 pF
In hold mode 4
IIL Input leakage current ±1 µA
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range 2.5 5 V
IREF Reference input current Average current, VREF = 5 V,
2-kHz, full-scale input,
throughput = 2.5 MSPS		 1.3 mA
DC ACCURACY
Resolution 16 Bits
NMC No missing codes 16 Bits
INL Integral nonlinearity TA = –40°C to +85°C –0.6 ±0.25(2) 0.6 LSB(3)
TA = –40°C to +125°C –0.7 ±0.25(2) 0.7
DNL Differential nonlinearity TA = –40°C to +85°C –0.6 ±0.25(2) 0.6 LSB
TA = –40°C to +125°C –0.7 ±0.25 0.7
E(IO) Input offset error –1 ±0.025(2) 1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GE Gain error –0.02 ±0.01(2) 0.02 %FS
GE/dT Gain error thermal drift 0.25 ppm/°C
Transition noise 0.35 LSB
CMRR Common-mode rejection ratio At dc to 20 kHz 80 dB
AC ACCURACY(4)
SINAD Signal-to-noise + distortion fIN = 2 kHz 94.4 96 dB
fIN = 100 kHz 95
fIN = 500 kHz 83.9
SNR Signal-to-noise ratio fIN = 2 kHz 94.5 96 dB
fIN = 100 kHz 95.9
fIN = 500 kHz 84
THD Total harmonic distortion(5) fIN = 2 kHz –118 dB
fIN = 100 kHz –102
fIN = 500 kHz –101
SFDR Spurious-free dynamic range fIN = 2 kHz 120 dB
fIN = 100 kHz 108
fIN = 500 kHz 106
DIGITAL INPUTS(6)
VIH High-level input voltage 0.65 DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.35 DVDD V
DIGITAL OUTPUTS(6)
VOH High-level output voltage IOH = 2-mA source DVDD – 0.45 V
VOL Low-level output voltage IOH = 2-mA sink 0.45 V
POWER SUPPLY
AVDD Analog supply voltage 1.65 1.8 1.95 V
DVDD Digital supply voltage 1.65 1.8 1.95 V
IDD AVDD supply current
(AVDD = 1.8 V)		 Active, 2.5-MSPS throughput,
TA = –40°C to +85°C		 5 6.5 mA
Active, 2.5-MSPS throughput,
TA = –40°C to +125°C		 5 6.75
Static, ACQ state 3.7 mA
Low-power, NAP mode 500 µA
Power-down, PD state 1
PD AVDD power dissipation
(AVDD = 1.8 V)		 Active, 2.5-MSPS throughput,
TA = –40°C to +85°C		 9 11.7 mW
Active, 2.5-MSPS throughput,
TA = –40°C to +125°C		 9 12.15
Static, ACQ state 6.6 mW
Low-power, NAP mode 900 µW
Power-down, PD state 1.8
TEMPERATURE RANGE
TA Operating free-air temperature –40 125 °C
(1) Ideal input span, does not include gain or offset errors.
(2) See Figure 5-9, Figure 5-10, Figure 5-25, and Figure 5-26 for statistical distribution data for INL, DNL, offset, and gain error parameters.
(3) LSB = least-significant bit. 1 LSB at 18 bits is approximately 3.8 ppm.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.1 dB below full-scale, unless otherwise specified.
(5) Calculated on the first nine harmonics of the input frequency.
(6) As per the JESD8-7A standard. Specified by design; not production tested.