A data transfer frame between the device and the host controller is bounded between a CS falling edge and the subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 6-11) at any time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is a function of relative timing between the CONVST and CS signals.

Figure 6-11 Data Transfer Frame

For this discussion, assume that the CONVST signal remains low.

For a typical data transfer frame F:

1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
   • RVS goes low, indicating the beginning of the data transfer frame.
   • The SCLK counter is reset to 0.
   • The device takes control of the data bus. As shown in Figure 6-11, the 20-bit contents of the output data word (see Figure 6-9) are loaded in to the 20-bit ODR (see Figure 6-5).
   • The 20-bit IDR (see Figure 6-5) is reset to 00000h, corresponding to a NOP command.
2. During the frame, the host controller provides clocks on the SCLK pin:
   • On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted in to the IDR.
   • On each launch edge of the output clock (SCLK in this case), ODR data are shifted out on the selected SDO-x pins.
   • The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section).
3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
   • The SDO-x pins go to tri-state.
   • RVS goes high (after a delay of t_{d_RVS}).
   • As illustrated in Figure 6-11, the 20-bit contents of the IDR are transferred to the command processor (see Figure 6-5) for decoding and further action.

After pulling CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the t_{d_RVS} time (see the Timing Requirements: SPI-Compatible Serial Interface table) to elapse before initiating a new operation (data transfer or conversion). The delay, t_{d_RVS}, for any data transfer frame F varies based on the data transfer operation executed in the frame F.

At the end of the data transfer frame F:

• If the SCLK counter is < 20, it indicates that IDR has captured less than 20 bits from the SDI. In this case, the device treats the frame F as a short command frame. At the end of a short command frame, the IDR is not updated and the device treats the frame as a no operation command.
• If the SCLK counter = 20, it indicates that the IDR has captured exactly 20 bits from SDI. In this case, the device treats the frame F as a optimal command frame. At the end of an optimal command frame, the command processor decodes the 20-bit contents of the IDR as a valid command word.
• If the SCLK counter > 20, it indicates that the IDR captured more than 20 bits from the SDI, and only the last 20 bits are retained. In this case, the device treats the frame F as a long command frame. At the end of a long command frame, the command processor treats the 20-bit contents of the IDR as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, as explained above, the last 20 bits shifted into the device prior to the CS rising edge must constitute the desired command.

In a short command frame, the write operation to the device is invalidated, however, the output data bits transferred during the frame are still valid output data. Therefore, the host controller can use such shorter data transfer frames to read only the required number of MSB bits from the 20-bit output data word. As shown in Figure 6-9, an optimal read frame for ADS9120 needs to read only the 16 MSB bits of the output data word. The length of an optimal read frame depends on the output protocol selection; refer to the Protocols for Reading From the Device section for more details.