SBAS905C November 2019 – July 2020 ADS8686S
PRODUCTION DATA
The ADS8686S supports on-chip register access in software mode. A single register read command is performed by a two 16-bit parallel data access through the parallel bus (DB15 to DB0), CS, WR, and RD signals. See the Section 7.6 section to determine the data to be driven on the DB[15:0] pins. Pull the CS pin low to take the DB[15:0] pins out of high-impedance state. Pull the WR pin low to configure the DB[15:0] pins as digital input. The host drives the DB[15:0] pins with the data to enable read operation for the register selected. Pull the WR pin high. The register address is latched into the device on the rising edge of WR. The device transfers the register data to the output register. Pull the RD pin low to configure the DB[15:0] pins as digital outputs. The device outputs the register content on the DB[15:0] pins. The host can read the data on the rising edge of the RD pin. Figure 7-25 shows the parallel register read timing diagram.