SBASAS5 October   2025 AMC0100R

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (DEN Package)
    5. 5.5 Package Characteristics
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagram
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Isolation Channel Signal Transmission
      3. 6.3.3 Analog Output
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Shunt Resistor Sizing
        2. 7.2.2.2 Input Filter Design
        3. 7.2.2.3 Designing the Bootstrap Supply
        4. 7.2.2.4 Connecting the REFIN Pin
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output signal rise time 1.7 µs
tf Output signal fall time 1.7 µs
VINx  to VOUTx signal delay (50% - 10%) Unfiltered output 0.8 1.3 µs
VINx  to VOUTx signal delay (50% - 50%) Unfiltered output 1.6 2.1 µs
VINx  to VOUTx signal delay (50% - 90%) Unfiltered output 2.5 3 µs
tAS Analog settling time VDD1 step to 3.0V with VDD2 ≥ 3.0V, VREFIN = 3.3V, to VOUT valid, 0.1% settling 30 100 µs