SBASB14B October   2024  – October 2025 AMC0311S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information (D Package)
    5. 6.5  Thermal Information (DWV Package)
    6. 6.6  Power Ratings 
    7. 6.7  Insulation Specifications (Basic Isolation)
    8. 6.8  Insulation Specifications (Reinforced Isolation)
    9. 6.9  Safety-Related Certifications (Basic Isolation)
    10. 6.10 Safety-Related Certifications (Reinforced Isolation)
    11. 6.11 Safety Limiting Values (D Package)
    12. 6.12 Safety Limiting Values (DWV Package)
    13. 6.13 Electrical Characteristics
    14. 6.14 Switching Characteristics
    15. 6.15 Timing Diagram
    16. 6.16 Insulation Characteristics Curves
    17. 6.17 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
      4. 7.3.4 Reference Input
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Connecting the REFIN Pin
      3. 8.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.13 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0V to 5.5V, VDD2 = 3.0V to 5.5V, REFIN = GND2, SNSN = GND1, VINP = 0.25V to 2.25V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5V, and VDD2 = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
CIN Input capacitance 2 pF
RINP Input impedance INP pin to GND1 0.05 2.4 GΩ
IIB, INP Input bias current(1) INP pin, INP = GND1 –10 ±3 10 nA
CMTI Common-mode transient immunity 150 V/ns
REFERENCE INPUT
IREFIN DC current out of REFIN pin VREFIN = 300mV, TA = 25℃ 3.7 4.45 5.2 µA
VREFIN = 450mV, TA = 25℃ 3.2 3.85 4.5
TCIREFIN Input impedance thermal drift 235 ppm/℃
ANALOG OUTPUT
Nominal gain 1 V/V
VOUT, SAT Output saturation voltage INP = GND1, VREFIN = 3.3V,
IOUT = –1mA (sinking)		 150 mV
ROUT Output resistance <0.2 Ω
Output short-circuit current sourcing or sinking,
INP = GND1, output shorted to
either GND2 or VDD2		 11 mA
DC ACCURACY
VOS Input offset voltage(1)(2) VOS = (VOUT – VREFIN),
INP = SNSN = GND1,
VREFIN = 250mV, TA = 25°C		 –1 ±0.15 1 mV
TCVOS Input offset thermal drift(1)(2)(4) –30 ±3 30 µV/°C
EG Gain error(1) TA = 25℃ –0.25% ±0.04% 0.25%
TCEG Gain error drift(1)(5) –50 ±5 50 ppm/°C
Nonlinearity –0.08% ±0.002% 0.08%
Output noise INP = GND1, BW = 50kHz 180 µVRMS
PSRR Power-supply rejection ratio(2) VDD1 DC PSRR, VINP = 250mV,
VDD1 from 3V to 5.5V		 –77 dB
VDD1 AC PSRR, VINP = 250mV,
VDD1 with 10kHz / 100mV ripple		 –59
VDD2 DC PSRR, VINP = 250mV,
VDD2 from 3V to 5.5V		 –100
VDD2 AC PSRR, VINP = 250mV,
VDD2 with 10kHz / 100mV ripple		 –69
AC ACCURACY
BW Output bandwidth 120 145 kHz
THD Total harmonic distortion(3) VINP = 2VPP, VINP > 0V,
fIN = 10kHz		 –83 –73 dB
SNR Signal-to-noise ratio VINP = 2.25VPP, fINP = 1kHz, BW = 10kHz 75 80 dB
VINP = 2.25VPP, fINP = 10kHz, BW = 50kHz 70
POWER SUPPLY
IDD1 High-side supply current 4.4 5.6 mA
IDD2 Low-side supply current 4.8 7.4 mA
VDD1UV High-side undervoltage detection threshold VDD1 rising 2.4 2.6 2.8 V
VDD1 falling  1.9 2.05 2.2
VDD2UV Low-side undervoltage detection threshold VDD2 rising 2.3 2.5 2.7 V
VDD2 falling 1.9 2.05 2.2
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106