SBASB35 January   2025 ADS8661W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.8 ADC Transfer Function

The device supports single-ended and differential inputs supporting both bipolar and unipolar input ranges. The output of the device is in straight-binary format for both bipolar and unipolar input ranges.

Figure 6-15 shows the ideal transfer characteristic for all input ranges. The full-scale range (FSR) for each input signal is equal to the difference between the positive full-scale (PFS) and the negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 212. For a reference voltage of VREF = 4.096V, Table 6-4 lists the LSB values corresponding to the different input ranges.

ADS8661W Device Transfer Function (Straight-Binary Format) Figure 6-15 Device Transfer Function (Straight-Binary Format)
Table 6-4 ADC LSB Values for Different Input Ranges (VREF = 4.096V)
INPUT RANGE POSITIVE FULL-SCALE (V) NEGATIVE FULL-SCALE (V) FULL-SCALE RANGE
(V)		 LSB
±3V × VREF 12.288 –12.288 24.576 6mV
±2.5V × VREF 10.24 –10.24 20.48 5mV
±1.5V × VREF 6.144 –6.144 12.288 3mV
±1.25V × VREF 5.12 –5.12 10.24 2.5mV
±0.625V × VREF 2.56 –2.56 5.12 1.25mV
0V to 3V × VREF 12.288 0 12.288 3mV
0V to 2.5V × VREF 10.24 0 10.24 2.5mV
0V to 1.5V × VREF 6.144 0 6.144 1.5mV
0V to 1.25V × VREF 5.12 0 5.12 1.25mV