SBAU352 June   2020 ADS131B04-Q1

 

  1.   ADS131B04-Q1 Evaluation Module
    1.     Trademarks
    2. 1 EVM Overview
      1. 1.1 ADS131B04-Q1EVM Kit
      2. 1.2 ADS131B04-Q1EVM Board
    3. 2 EVM Analog Interface
      1. 2.1 ADC Analog Input Signal Path
      2. 2.2 ADC External Clock (CLKIN) Options
    4. 3 Digital Interface
      1. 3.1 SPI Communication
      2. 3.2 Connection to the PHI
      3. 3.3 Digital Header
      4. 3.4 LaunchPad Connectors
    5. 4 Power Supplies
    6. 5 ADS131B04-Q1EVM Initial Setup
      1. 5.1 Default Jumper Settings
      2. 5.2 EVM Graphical User Interface (GUI) Software Installation
    7. 6 ADS131B04-Q1EVM Operation
      1. 6.1 EVM GUI Global Settings for ADC Control
      2. 6.2 Register Map Configuration Tool
      3. 6.3 Time Domain Display Tool
      4. 6.4 Spectral Analysis Tool
      5. 6.5 Histogram Tool
    8. 7 ADS131B04-Q1EVM Bill of Materials, PCB Layout, and Schematic
      1. 7.1 Bill of Materials
      2. 7.2 PCB Layout
      3. 7.3 Schematic

3.3 Digital Header

In addition to the PHI, the EVM has a header connected to the digital lines that can be used to connect a logic analyzer or oscilloscope. This placement allows for easy access to the digital communications. Header J6 is connected to the digital lines between the ADS131B04-Q1 and the PHI connector. Table 6 describes the digital header pins.

Table 6. Digital Header Pins

ADS131B04-Q1 Pin Name Digital Header Pin
SYNC/RESET J6[1]
DIN J6[2]
CLK J6[3]
CS J6[4]
SCLK J6[5]
DRDY J6[6]
DOUT J6[7]
GND J6[8]