SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

15 Set up ZCU102 Board Interface for VADJ_FMC

To set the ZCU102 board interface for VADJ_FMC, follow these steps:

  1. Execute the ZCU102-Board User Interface software (available for download from Xilinx.com).
  2. Select the appropriate COM Port to enable communication between the onboard MSP430 of the ZCU102 and the PC. This software is required to turn on the FMC_AUX supply of 1.8 V for the FMC bank of FPGA (see Figure 15-1).
    GUID-20220914-SS0I-R5HP-VKBV-TW7BXPVPZKQ5-low.pngFigure 15-1 ZCU102 Board User Interface
  3. Select the Set VADJ to 1.8 V check box (see Figure 15-2).
    GUID-20220914-SS0I-X7JC-5KXM-5XPQN886PWDG-low.pngFigure 15-2 Setting VADJ
  4. Confirm the same by reading the VADJ_FMC voltage. The voltage value must be 1.80 V (see Figure 15-3).
    GUID-20220914-SS0I-RWVQ-VLBG-RQBPZLKWB7B3-low.pngFigure 15-3 VADJ_FMC Voltage